DDIO clock timing

[Altera_Forum]

Hi,  

 I'm using a Stratix III EP3SL340 C3 (Terasic DE3) and I had a question about DDIO.  I have 12 bit data from an ADC (AFE5807) coming in at 80MSPS. I wanted to use DDIO to receive the data. I'll serialize it later.  I wanted to ask how to specify the constraints for the input. e.g. I have input lines lvds[8..0]  Data from 8 channels is coming in DDR on lvds[7..0] And the DDR clock at 480MHz is on lvds[8]. This will clock the DDIO blocks of lvds[7..0]  How do I tell quartus all this in the sdc file to do its magic?  Thanks Zubair

[Altera_Forum]

I am going through this. http://www.alterawiki.com/uploads/3/3f/timequest_user_guide.pdf 

 But its taking time..  My main question should be. A few pointers would help. And where do I look if this is possible even. The Stratix III handbook says that the DDIO doesn't have a limit itself. But it depends on the clock source. And I am not sure about the clock limit..  Cheers Zubair

[Altera_Forum]

The best way to see if this is possible or not is to create a simple, mock-up, design and run it through TimeQuest. 

But the maximum possible clock frequency is usually listed in the "DC and switching characteristics" part of the device's Handbook. The slower grades of Stratix III might not do what you need.  You should also read the DDR Timing cookbook: http://www.alterawiki.com/wiki/ddr_timing_with_timequest

[Altera_Forum]

Thank-you rbugalho. I found another great resource as well. 

 For those stumbling accross this post later on.  http://www.ti.com/lit/an/slaa545/slaa545.pdf is a document by TI for interfacing a 250MSPS ADC and DAC with a Stratix IV using ALT DDIO blocks via the LVDS physical interface.   Explains the timing relations, clocks, phase relations, constraints etc really well.  Cheers Zubair