Synthesizable vs non-synthesizable code

[Altera_Forum]

Hi, 

 I have a question regarding how the below piece of code can be made synthesizable. The simulation works fine in modelsim. But when I run Analysis and Synthesis in Quartus I get the following warning : warning (10034): output port at <> has no driver . The warning is shown because this : if (sig == 5'b11111) cannot be mapped on to any hardware on the FPGA right?? Please correct me if I am wrong.   ( sig ---> is an internal wire output ---> is an output port )  if (sig == 5'b11111) begin  output <= 2'd1; end  Any suggestions will be of great help.  Thank you.

[Altera_Forum]

The whole purpose of logic design is to take input(s) from outside module and drive output(s) to other modules and according to your internal logic decisions. 

I am not aware if an input-less design is ever possible in fpgas. Moreover if your outputs are driven once only and undefined otherwise then the compiler simply is saying you don't need to do anything and the output stays floating with any empty fpga. So at least get clock input, then an internal counter and drive output based on count value assigning to it high or low.

[Altera_Forum]

Thanks for the reply Kaz.. I should have been more articulate when I asked the question . It was just a portion of the code that I had written above and not the code itslef. My code is more like this...  

 <verilog statements> .... ... always (@posedge clock) begin  if (sig_1 == 5'b11111)  begin   output <= 2'd0;  end    else if (sig_2 == 5'b11111)  begin   output <= 2'd1;  end    else if (sig_3 == 5'b11111)  begin   output <= 2'd2;  end  end ...... ..... <verilog statements>  This 'output' signal is connected to the input of another module. And I am getting this warning msg : warning (10034): output port at <> has no driver .

[Altera_Forum]

I can't see anything wrong with your above part of code.  

The issue must be somewhere else in those sig_1, sig_2, sig_3 and it is likely they are never driven to the values of 11111

[Altera_Forum]

Yeah the values for sig_1, sig_2, sig_3 are calculated based on the inputs and only based on the inputs can we know whether they are equal to 11111 or not. So during synthesis when no test bench is applied the values of the sig_1, sig_2, sig_3 is not known and hence the 'output' signal cannot be assigned with anything. Hence the warning message (10034): output port at <> has no driver .  

 So once input vectors are given to the design it should be able to calculate all the values and assign 'output' with some value cuz the simulation is working fine in modelsim. Will the hardware work fine once its driven with inputs? Can you kindly let me know if I should ignore the warning (10034) message during synthesis ?   Thanks a lot for your help.

[Altera_Forum]

--- Quote Start ---  Yeah the values for sig_1, sig_2, sig_3 are calculated based on the inputs and only based on the inputs can we know whether they are equal to 11111 or not. So during synthesis when no test bench is applied the values of the sig_1, sig_2, sig_3 is not known and hence the 'output' signal cannot be assigned with anything. Hence the warning message (10034): output port at <> has no driver .   So once input vectors are given to the design it should be able to calculate all the values and assign 'output' with some value cuz the simulation is working fine in modelsim. Will the hardware work fine once its driven with inputs? Can you kindly let me know if I should ignore the warning (10034) message during synthesis ?   Thanks a lot for your help.  --- Quote End ---    You don't actually need to specifically drive sig_1,sig_2,sig_3 for synthesis but they should be either inputs to your module or if internal be dependent on some other inputs. As long as the design has inputs then it implies the tool will know they could be any value.  you cannot ignore the warning as it means synthesis sets output floating(no connection). It will help to see your module interface and how these signals are driven.

[Altera_Forum]

Hello kaz, 

 Since I cannot attach the original code I have written something very similar to it and I have attached it. The module test.v is the one under question.  The wires wire1, wire2, wire3 are directly dependent on the inputs where as test_out is dependent on wire1, wire2, wire3.  Kindly let me know your thoughts on this.  Thank you.

[Altera_Forum]

--- Quote Start ---  Since I cannot attach the original code I have written something very similar to it and I have attached it.  --- Quote End ---   The code example doesn't generate a "no driver" warning, thus it's apparently not similar.  There are no obvious problems in the code.