Configuring quartus options for better AOC compilation flow

[Altera_Forum]

I have some experience with the MaxelerOS and configuration of the compilation flow executed by ISE. Namely, in specific phases of the process it is possible to employ several hardware threads at once, for instance several cost tables can be tested in parallel and we can set a limit to the number of cost tables so that the process may fail only after a reasonable number of tables has been tested. 

 Is there any way to configure the quartus environment or the TCL scripts of the generated project in order to speed up the generation of the aocx design file? Sometimes my design fails and I don't really know where to search for finding what is causing the error. Should I open the project in quartus and look around? Is the error logged in the quartus_sh_compile.log? I find that sometimes it is, sometimes it is not.  Is there a structured way to address compilation errors, specifically those which happen in the compilation phase and not in the RTL generation phase?   Thank you.

[Altera_Forum]

Typically I look at the log files first (starting at the bottom of the file and working my way up) and then if I don't spot the issue I open the Quartus project that was generated by the OpenCL compiler. Sometimes I go as far as opening up the Qsys system within the hardware project and making sure that the kernel block is instantiate and connected properly and also making sure the Qsys settings are correct. When you come across cryptic failures go ahead and file a service request with Altera so that the error reporting can be improved or bugs.