module instantiation

[Altera_Forum]

Hey, 

 I am a newbie in verilog and FPGA. I have three modules which I am trying to connect using verilog. The three modules are clock divider, which divides the 50 Mhz clock into 1 hz. Then i have a up counter. Third block is hexadecimal to seven segment decoder, which will count from 00 to FF(hex). I am looking for examples in internet but I didn't find any concrete examples. It will be great if some one can explain me or guide towards an example which has module instantiation or somebody wants to see my source code I could happily post if someone can help me joining them.  Regards Muzz

[Altera_Forum]

Instanstiating a module in verilog is very simple, just call the module with instance name. 

google it then u can get a lot of example

[Altera_Forum]

--- Quote Start ---  Instanstiating a module in verilog is very simple, just call the module with instance name. google it then u can get a lot of example  --- Quote End ---    I know its pretty simple. But the thing is I am not able to grasp the idea of it. What specifically do we mean by instance name? Can you explain me with an example. i will be grateful to you.  Regards muzz

[Altera_Forum]

Spend some time on this site: http://www.asic-world.com/verilog/

[Altera_Forum]

--- Quote Start ---  Spend some time on this site: http://www.asic-world.com/verilog/  --- Quote End ---    thanks for the link !!!

[Altera_Forum]

I think it is great to go through the latest system verilog standard, there are a lot of fancy feature added: 

 http://standards.ieee.org/getieee/1800/download/1800-2012.pdf