Counter to find the delay between a radar and an object

Altera_Forum · ‎07-25-2013

Good evening,

I am doing a project to measure a distance between a Radar and an object. I am sending a pulse throw the FPGA (DE0-nano) to the radar and I am receiving the signal echo in the FPGA again. I want to measure the delay between the sending signal and the received echo in HW because the delay is about 30 nanoseconds from distance starting in 5 meters.

Can anyone help me please to find out how to measure that delay!?

Thanks in advance and please give me some ideas because I'm really desperate :(:(:(.

Altera_Forum · ‎07-25-2013

choose a fast clock e.g. 400MHz and run counter from sending moment to receiving moment.

you need to take into account delay through any DAC/ADC and your own logic.

Altera_Forum · ‎07-25-2013

Yes, I need to use an ADC to receive the echo signal, but I am not seeing how can I do it to do the counter!?

I need to start the counter I send the pulse and stop it when I receive some information in the ADC and don't know how to do it.

Altera_Forum · ‎07-25-2013

I thought you are sending and receiving the pulse. Anyway that is another issue then. You need to send high frequency signal (On/OFF) e.g. 20 MHz or so. You need generate that from an NCO and pass i to DAC then some RF guy may help push it up to the air, receive it for you and pass it to ADC. Then you design some logic to detect the sine wave (possibly flooded with noise now). You can detect it based on some criteria e.g. amplitude threshold(and this follows gain at DAC...etc).

For an FPGA engineer, the logic part is not difficult. The RF side is.

Altera_Forum · ‎07-25-2013

Maybe I am not explaining myself in the better way :X

I have a DE0-nano FPGA that sends a pulse, a RADAR receive it and send it, and then I receive the echo signal in my ADC that is inside the FPGA (there is no DAC in this FPGA).

My purpose is to measure the delay between the sending signal and the received signal in the ADC. My question is how can I do it in VHDL or maybe with DSP-Builder.

Thanks

Altera_Forum · ‎07-25-2013

Do you have any pulse triggered by transmitter that informs fpga about start of pulse. Then use that to start a counter.

On the ADC side you will receive a signal and you can directly check if amplitude passed a certain threshold then stop counter.

The count value would indicate delay in periods(so smaller period = better resolution) but yo need to subtract delays caused by your system if you are after measuring absolute delays(not so if relative delay is your target)

Altera_Forum · ‎07-25-2013

"Do you have any pulse triggered by transmitter that informs fpga about start of pulse" was this a question? If yes, I don't know how can I inform the FPGA that I sent the pulse.

On the ADC side, how can I check if the amplitude passed a certain threshold to stop the counter?

Thanks

Altera_Forum · ‎07-25-2013

I am not familiar with your board. you will need to know when a pulse is sent to radar either by fpga triggering it or being informed.

On the ADC side, you receive digital signal and then you can check the values on each clock edge if it passed a given threshold. That threshold is matter of design details that you need to study and work out or experiment with your system.

Here is a chunk of code that may help

 --pseudocode
if reset = '1' then
    counter_en <= '0';
    counter <=0;
elsif rising_edge(clk) then
   if trigger = '1' then
      counter_en <= '1';
   end if;
   if adc_value > threshold then
      counter_en <= '0';
   end if;
   if counter_en = '1' then
      counter <= counter + 1;
   end if;
end if;

Altera_Forum · ‎07-25-2013

Thanks for your replies :D

It may help to try to find a way to do it!

Altera_Forum · ‎07-26-2013

ADC on DE0-nano has a maximum sampling rate of 200 kS/s, so it's not suitable to measure radar time-of-flight.

For a digital input signal, a resolution in a 1.5 ns range is feasible with a single clock and double data rate technique. Higher resolution optionally with phase shifted clocks.

Altera_Forum · ‎07-26-2013

Good afternoon FvM,

so that means that I can't measure the delay between a sending pulse from FPGA and the received pulse in ADC from FPGA?

there is anyway for me to send a pulse with the FPGA and receive his echo and measure this delay between signals?

Thanks

Altera_Forum · ‎07-26-2013

The received signal must be converted to a digital signal, e.g. by a comparator.

Altera_Forum · ‎07-26-2013

And it is converted with the ADC from the DE0-nano. Or it's not suitable?