Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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timequest report timing and quartus II compilation report

Altera_Forum
Honored Contributor II
1,187 Views

Hi, 

My design did not meet timing. So, I used the DSE to meet the timing of the design. 

 

I used those options in the quartus II compiler and ran the full compilation. 

The compilation showed timing violation for the slow and fast -900 mv 0C process corner and timing was met for 900mv 85C. 

 

So i right clicked the timing violation and opened report timing dialog box to see the paths for the violations. The report in the timing analyzer 

does not show any violated paths.  

 

Is there a bug in the compilation report or am i doing something wrong. I would appreciate your help. 

 

Thanks, 

Abdullah ansari
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Altera_Forum
Honored Contributor II
366 Views

it could be hold time or recovery violations, have you checked those too?

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Altera_Forum
Honored Contributor II
366 Views

Hi, 

Thank you for the reply. 

Yes, there are setup and hold time violations reported in the compilation report for the slow 900 mv 0c and fast 900 mv 0c model but no violations for the slow 900mv 85c model. But when i try to open the timing report by right clicking both the setup and hold violations, no violations are found in the timequest analyzer gui.
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Altera_Forum
Honored Contributor II
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After opening the Timing Analyzer double click under "Tasks" on the left side on "Set Operation Conditions..." and select the conditions you want to analyze the timing model in.

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