Analyzing Simulation result

[Altera_Forum]

Hello Friends, 

Am new to the Quartus II environments, but i like to know what a the specific part of the software one should go to and dwell on in other to analyse simulation result or output.

[Altera_Forum]

Quartus is for synthesis, while Modelsim is for simulation. 

 Here's a tutorial that uses both simulation and synthesis, including code and Tcl scripts to setup both simulation and synthesis  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  Cheers, Dave

[Altera_Forum]

Thanks Dave, i don't have Modelsim installed on my system, but Quartus does produces a logic output... i'm also aware it's output could be viewed as text. That's what am interested in.

[Altera_Forum]

--- Quote Start ---   i don't have Modelsim installed on my system   --- Quote End ---   Altera has a free version; Modelsim Altera Edition. Download it and install it.    --- Quote Start ---   but Quartus does produces a logic output... i'm also aware it's output could be viewed as text. That's what am interested in.  --- Quote End ---   Viewing generated code is a waste of your time.   Write VHDL or Verilog, then write a testbench, and confirm the tests pass in Modelsim.  Synthesize the design, along with timing and pin constraints, and generate an output netlist.  If timing passes, then run a simulation with the post-place-and-route netlist. Once you have confidence in your design skills, you can generally believe that a design that passes timing can be tested directly in hardware (since post-P&R simulation can take a while).  Bottom line is you do not need to read anything Quartus generates. Let *Modelsim* do that for you, and let a computer (via your testbench) test the code too.  Cheers, Dave