Error CODE VHDL in Structural model

[Altera_Forum]

Hi All. 

I am new VHDL and I see a error when coding: Can YOU help me! Error (10348): VHDL type mismatch error at DDS_test.vhd(37): type of formal parameter "out_cos" does not match port type of value Error (10482): VHDL error at DDS_test.vhd(37): object "bcd" is used but not declared Error (10558): VHDL error at DDS_test.vhd(37): cannot associate formal port "out_cos" of mode "object" with an expression Error (10346): VHDL error at DDS_test.vhd(35): formal port or parameter "bcd" must have actual or default value Error (10784): HDL error at DDS_test.vhd(25): see declaration for object "bcd"  -------------------------------- -------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL;  entity DDS_test is  port(  clk: in std_logic;  rst: in std_logic;  enb : in std_logic;  HEX: out std_logic_vector(20 downto 0)  ); end DDS_test; architecture bv of DDS_test is  signal out_cos: std_logic_vector(11 downto 0);  component DDS_cos port(  clk: in std_logic;  enb: in std_logic;  rst: in std_logic;  out_cos: out std_logic_vector(11 downto 0));  end component; component test port(  clk : in std_logic;  bcd : in std_logic_vector(3 downto 0); --BCD input  Segs : out std_logic_vector(6 downto 0) -- 7 bit decoded output.  );  end component; begin  DDScos: DDS_cos port map (  clk=>clk,  rst=>rst,  enb=>enb,  out_cos=>out_cos);  test1: test port map (  clk=>clk,  out_cos(3 downto 0)=>bcd,  Segs=>HEX(6 downto 0));  test2: test port map (  clk=>clk,  out_cos(7 downto 4)=>bcd,  Segs=>HEX(13 downto 8));  test3: test port map (  clk=>clk,  out_cos(11 downto 8)=>bcd,  Segs=>HEX(20 downto 14));  end bv;   THANKS SO MUCH!

[Altera_Forum]

I found errors! 

^^ tks