half-band filter implementation

[Altera_Forum]

I know this is typical in signal processing implementation. Therefore, is there already an example on how to implementation a half-band filter in Verilog? Thanks in advance.

[Altera_Forum]

What's wrong with the answer Google would have given you ... ? 

 http://www.dsprelated.com/showarticle/124.php  Sure its for Xilinx, but you can figure out the differences ...

[Altera_Forum]

Is there a corresponding function from Altera for "DDC_HF2_DSP" in the following code for xilinx? 

 //* (A+D)*B+C //14 pipelines genvar Num; generate  for (Num = 0; Num <= 11; Num = Num + 1)   begin : U_DDC_HF2_DSP  DDC_HF2_DSP DDC_HF2_DSP  (  //* Inputs  .clk ( Clk ),  .a ( Add_a[Num] ),  .d ( Add_d[Num] ),  .b ( Mult_b[Num] ),  .c ( Add_c[Num] ),  //* Outputs   .p ( Dsp_r[Num] )  );  end endgenerate

[Altera_Forum]

--- Quote Start ---  Is there a corresponding function from Altera for "DDC_HF2_DSP" in the following code for xilinx?  //* (A+D)*B+C //14 pipelines genvar Num; generate  for (Num = 0; Num <= 11; Num = Num + 1)   begin : U_DDC_HF2_DSP  DDC_HF2_DSP DDC_HF2_DSP  (  //* Inputs  .clk ( Clk ),  .a ( Add_a[Num] ),  .d ( Add_d[Num] ),  .b ( Mult_b[Num] ),  .c ( Add_c[Num] ),  //* Outputs   .p ( Dsp_r[Num] )  );  end endgenerate  --- Quote End ---    That is just xilinx mult add (a bit more configurable than altera).   In principle you need to multiply and add input stages with coeffs(sum of products). You can use direct structure or transposed.  For halfband single rate with coeffs 1~11 : multiply coeffs(1,3,5,6,7,9,11) with their input stages and add up to get (y1) and so on  as such you need 7 mults coeff 6 if 2^n then just insert leading n zeros, thus you need 6 mults only  implementation is based on a pipe of 11 stages with mults connected every other coeff then all results added and truncated back. That is all.  since this filter is symmetrical you can also pre add two stages and multiply by its coeff thus you can reduce mults to 3