error 10170 expecting identifier ,;

[Altera_Forum]

i got the following errors for the code i developed 

 Error (10170): Verilog HDL syntax error at arbiter_for_8_clients.v(59) near text "("; expecting an identifier Error (10170): Verilog HDL syntax error at arbiter_for_8_clients.v(59) near text ")"; expecting ";"   59 for (i= (last_served_port+1),((gnt_valid==0)&&(i<=8)),i=i+1)  if(port_req[i]==1) begin  gnt_port=i;  gnt_valid=1;  end   Please suggest the corrections to be made. Thanks

[Altera_Forum]

well.. this is the first program i have tried to execute after installing quartus on the system.

[Altera_Forum]

it looks like you are trying to approach Verilog more like software than hardware based on the use of gnt_valid. read up on for loops in Verilog

[Altera_Forum]

If this is your 1st program using then the generate for loop wouldn't be the 1st thing to do. I suggest try blinking a led- its challenging enough for 1st time. 

Anyhow the code is not following the correct syntax and from the looks of it you do not understand what the for loop does in verilog. It is not like C++.  It more like a way to instantiate code without having to type alot. Verilog just unrolls the loop and executes everything in parallel.  Here is a link /w example of the generate for loop. http://www.asic-world.com/verilog/verilog2k2.html