"Node is missing source" error when working with busses

[Altera_Forum]

Hello again, 

 Working on another project for my ECE class. This one is a "tallyer." I've put the schematic below.  Basically, I am just wondering: for the bus line that runs from after the register to the A inputs of the adder, do I need to include input symbols? Intuition tells me no, since we are using Address[7..0] as the inputs for A[7..0] (as I have it wired in the schematic shown), but compiling the circuit results in errors saying "Node (whatever) is missing source" for A[7..0].   I've done the whole circuit with input symbols as well, and then I do not get these errors, but I am not sure if this is how it was intended to be made.  Any help would be great.  https://www.alteraforum.com/forum/attachment.php?attachmentid=7990

[Altera_Forum]

IIRC from schematics (its been a while, and everyone will avoid them where possible). you cannot connect a wire to a bus. You need named association. So disconnect the individual A wires but leave them named, and the compiler should do the association for you. 

 PS. Dont put too much energy into learning the schematic part of the tool. You're much much better off learning to do it in an HDL.

[Altera_Forum]

I agree with the suggestion. If you want to use schematic entry however, the signal names should be consistent, address[x] at both sides of the bus...