Controlling HPS EMAC from FPGA Fabric (Nios II)

[Altera_Forum]

I would like to know if the Ethernet port (EMAC0) can be controlled by the NIOS in the FPGA Fabric. From the documentation it seems possible but it is not 100% clear that this HPS peripheral can be used by the Nios instead of the ARM. I know that the FPGA Fabric has access to the EMAC CSR register through the L4 but can it be completely used by the Nios? Thanks

[Altera_Forum]

I don't know of anyone who has done that yet but the HPS was designed with that use case in mind. You'll want to make sure the interrupt line for the EMAC gets routed into the FPGA since Nios II should be servicing those interrupts and not the processors in the HPS block. To access the CSRs you'll want to put an address span expander (window bridge) between the Nios II core and the FPGA-to-HPS bridge so that you only expose a subset of the 4GB address space to the Nios II data master.

[Altera_Forum]

Did you manage to get anywhere with controlling the EMAC from the FPGA fabric? We are thinking of doing something similar and it would be useful to know if you have managed to find a workable solution.