Unable to run simulation in Simulation Waveform Editor

[Altera_Forum]

Hello, I'm just starting to use Quartus for VHDL designs and I keep running into a problem while trying to run a simulation using a .vwf file in the Simulation Waveform Editor. Whenever my design infers a higher level component (such as the altsyncram in my example), I am unable to run a functional or a timing simulation without receiving the following error: 

   --- Quote Start ---  # ** Error: (vsim-3033) nofile(37): Instantiation of 'generic_m10k' failed. The design unit was not found.# # Region: /sim_tester_vlg_vec_tst/i1/\ram_rtl_0|auto_generated|ram_block1a0 # Searched libraries:# C:/altera/13.1/modelsim_ase/altera/verilog/cyclonev# C:/altera/13.1/modelsim_ase/altera/verilog/altera# C:/altera/13.1/modelsim_ase/altera/verilog/altera_mf# C:/altera/13.1/modelsim_ase/altera/verilog/220model# C:/altera/13.1/modelsim_ase/altera/vhdl/sgate# C:/altera/13.1/modelsim_ase/altera/verilog/cyclonev# Loading work.sim_tester_vlg_sample_tst# Loading work.sim_tester_vlg_check_tst# Error loading design Error loading design   Error.     --- Quote End ---    I wrote some simple code to use to try to figure this error out. The VHDL code I am using is as follows:  library IEEE; use IEEE.std_logic_1164.all; entity sim_tester is port(in1: in std_logic_vector(7 downto 0); clk, r_en, w_en: in std_logic; out1: out std_logic_vector(7 downto 0)); end sim_tester; architecture sim of sim_tester is type MemoryType is array(0 to 15) of std_logic_vector(7 downto 0); signal ram: MemoryType := (others => (others => '0')); signal w_addr: integer range 0 to 15 := 0; signal r_addr: integer range 0 to 15 := 0; begin process(clk) begin if clk'event and clk = '1' then if r_en = '1' then out1 <= ram(r_addr); elsif w_en = '1' then ram(w_addr) <= in1; end if; end if; end process; end sim;   From the error message, it seems like Quartus is not including all the libraries it needs when invoking Modelsim to do the simulation. I am not sure if that is an accurate observation, so help solving this in any direction would be greatly appreciated. I also attached the full log I received when attempting the simulation - this file includes the error message.  My Quartus set up is: Quartus II 64-bit Version 13.1.1 Build 166 11/26/2013 SJ Web Edition The simulation settings use ModelSim-Altera Version 10.1d

[Altera_Forum]

im like a dirty piglet always ask for help and never share so today decided to wash my sins. inside modelsim on a library window if you would expand all the libraries and then click ctrl+f and type there "generic_m10k" you would find that it is located into altera_insim_ver library. so go to the project window in modelsim and right click on empty space then add to project -> existed file. navigate into \altera\13.1\modelsim_ase\altera\verilog\src and find altera_lnsim.v file, add it to your current project. compile it along with other files that you are using. now,in modelsim go to simulate -> start simulation ->library ->add and type: altera_lnsim_ver click ok. this way you are telling modelsim to use this library you just compiled. personally i think it should be programmed so that libraries you compile must be automatically included into the use list but by unknown reasons developers left this for us to do. remember, to learn it i have spent tens of hours, tens of days, and tens of neurons when i was nervous because nothing worked, so mention my name in prayers when you go to the church :) tell the big guy i demand at least 1million to be happy :)))