IP Compiler for PCI express on Stratix IV

[Altera_Forum]

Hello, 

 it´s the first time that I am approaching to the PCI express interface. I would like to implement a simple data forwarding on my development board, but I have no clue where to start from. I have read the documentation about the IP Compiler Megacore but still it´s still not really clear to me how I can start implementing my design. The demo projects I have found on the alter website are not really clear to me and so I have decided to start from scratch. My idea ist to generate a logic, for a example a 64 bits counter, and use it to send data throught the IP Compilert, to the pins of my PCI express connector. The second step is reading the data from a MATLAB application in order to verify that the data are sent correctly. I have found some differences between the signals of the megacore used inside the example design, and the one generated by the plugin wizard. There are many signals which I don´t see there, like for instance app_int_sts or busy_altgxb_reconfig, just to mention a couple of them.  I would like to keep it really simple and get my application working, any clue or suggestion from someone more experienced than me?  I am working with a Stratix IV based development board, and using Quartus II 12.1.  BR,   Giovanni

[Altera_Forum]

Read the document posted with this thread: 

 http://www.alteraforum.com/forum/showthread.php?t=35678  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 thanks for your answer. I was reading the documentation which you have posted. It was useful to give me an idea about where to start, in order to start from scratch from a simple idea. After following all the steps of the tutorial I have launched analysis and synthesis in order to see how the design looked like, but Quartus complains about  Error (12006): Node instance "pcie" instantiates undefined entity "qsys_system_pcie" Error (12006): Node instance "dma" instantiates undefined entity "qsys_system_dma" Error (12006): Node instance "onchip_ram" instantiates undefined entity "qsys_system_onchip_ram" Error (12006): Node instance "pcie_bar0_translator" instantiates undefined entity "altera_merlin_master_translator" Error (12006): Node instance "dma_read_master_translator" instantiates undefined entity "altera_merlin_master_translator" Error (12006): Node instance "dma_write_master_translator" instantiates undefined entity "altera_merlin_master_translator" Error (12006): Node instance "onchip_ram_s1_translator" instantiates undefined entity "altera_merlin_slave_translator" Error (12006): Node instance "pcie_txs_translator" instantiates undefined entity "altera_merlin_slave_translator" Error (12006): Node instance "pcie_bar2_translator" instantiates undefined entity "altera_merlin_master_translator" Error (12006): Node instance "pcie_cra_translator" instantiates undefined entity "altera_merlin_slave_translator" Error (12006): Node instance "dma_control_port_slave_translator" instantiates undefined entity "altera_merlin_slave_translator" Error (12006): Node instance "pcie_bar0_translator_avalon_universal_master_0_agent" instantiates undefined entity "altera_merlin_master_agent" Error (12006): Node instance "dma_read_master_translator_avalon_universal_master_0_agent" instantiates undefined entity "altera_merlin_master_agent" Error (12006): Node instance "dma_write_master_translator_avalon_universal_master_0_agent" instantiates undefined entity "altera_merlin_master_agent" Error (12006): Node instance "onchip_ram_s1_translator_avalon_universal_slave_0_agent" instantiates undefined entity "altera_merlin_slave_agent" Error (12006): Node instance "onchip_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo" Error (12006): Node instance "pcie_txs_translator_avalon_universal_slave_0_agent" instantiates undefined entity "altera_merlin_slave_agent" Error (12006): Node instance "pcie_txs_translator_avalon_universal_slave_0_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo" Error (12006): Node instance "pcie_bar2_translator_avalon_universal_master_0_agent" instantiates undefined entity "altera_merlin_master_agent" Error (12006): Node instance "pcie_cra_translator_avalon_universal_slave_0_agent" instantiates undefined entity "altera_merlin_slave_agent" Error (12006): Node instance "pcie_cra_translator_avalon_universal_slave_0_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo" Error (12006): Node instance "dma_control_port_slave_translator_avalon_universal_slave_0_agent" instantiates undefined entity "altera_merlin_slave_agent" Error (12006): Node instance "dma_control_port_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo" Error (12006): Node instance "addr_router" instantiates undefined entity "qsys_system_addr_router" Error (12006): Node instance "addr_router_001" instantiates undefined entity "qsys_system_addr_router_001" Error (12006): Node instance "addr_router_002" instantiates undefined entity "qsys_system_addr_router_001" Error (12006): Node instance "id_router" instantiates undefined entity "qsys_system_id_router" Error (12006): Node instance "id_router_001" instantiates undefined entity "qsys_system_id_router_001" Error (12006): Node instance "addr_router_003" instantiates undefined entity "qsys_system_addr_router_003" Error (12006): Node instance "id_router_002" instantiates undefined entity "qsys_system_id_router_002" Error (12006): Node instance "id_router_003" instantiates undefined entity "qsys_system_id_router_002" Error (12006): Node instance "limiter" instantiates undefined entity "altera_merlin_traffic_limiter" Error (12006): Node instance "limiter_001" instantiates undefined entity "altera_merlin_traffic_limiter" Error (12006): Node instance "burst_adapter" instantiates undefined entity "altera_merlin_burst_adapter" Error (12006): Node instance "burst_adapter_001" instantiates undefined entity "altera_merlin_burst_adapter" Error (12006): Node instance "burst_adapter_002" instantiates undefined entity "altera_merlin_burst_adapter" Error (12006): Node instance "burst_adapter_003" instantiates undefined entity "altera_merlin_burst_adapter" Error (12006): Node instance "rst_controller" instantiates undefined entity "altera_reset_controller" Error (12006): Node instance "cmd_xbar_demux" instantiates undefined entity "qsys_system_cmd_xbar_demux" Error (12006): Node instance "cmd_xbar_demux_001" instantiates undefined entity "qsys_system_cmd_xbar_demux_001" Error (12006): Node instance "cmd_xbar_demux_002" instantiates undefined entity "qsys_system_cmd_xbar_demux_002" Error (12006): Node instance "cmd_xbar_mux" instantiates undefined entity "qsys_system_cmd_xbar_mux" Error (12006): Node instance "cmd_xbar_mux_001" instantiates undefined entity "qsys_system_cmd_xbar_mux_001" Error (12006): Node instance "rsp_xbar_demux" instantiates undefined entity "qsys_system_rsp_xbar_demux" Error (12006): Node instance "rsp_xbar_demux_001" instantiates undefined entity "qsys_system_cmd_xbar_demux_002" Error (12006): Node instance "rsp_xbar_mux_001" instantiates undefined entity "qsys_system_rsp_xbar_mux_001" Error (12006): Node instance "rsp_xbar_mux_002" instantiates undefined entity "qsys_system_rsp_xbar_mux_001" Error (12006): Node instance "cmd_xbar_demux_003" instantiates undefined entity "qsys_system_cmd_xbar_demux_003" Error (12006): Node instance "rsp_xbar_demux_002" instantiates undefined entity "qsys_system_rsp_xbar_demux_002" Error (12006): Node instance "rsp_xbar_demux_003" instantiates undefined entity "qsys_system_rsp_xbar_demux_002" Error (12006): Node instance "rsp_xbar_mux_003" instantiates undefined entity "qsys_system_rsp_xbar_mux_003" Error (12006): Node instance "width_adapter" instantiates undefined entity "altera_merlin_width_adapter" Error (12006): Node instance "width_adapter_001" instantiates undefined entity "altera_merlin_width_adapter" Error (12006): Node instance "width_adapter_002" instantiates undefined entity "altera_merlin_width_adapter" Error (12006): Node instance "width_adapter_003" instantiates undefined entity "altera_merlin_width_adapter" Error (12006): Node instance "irq_mapper" instantiates undefined entity "qsys_system_irq_mapper" Error (12006): Node instance "irq_synchronizer" instantiates undefined entity "altera_irq_clock_crosser" Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 57 errors, 3 warnings Error: Peak virtual memory: 611 megabytes Error: Processing ended: Tue Oct 15 18:28:03 2013 Error: Elapsed time: 00:00:13 Error: Total CPU time (on all processors): 00:00:03  looking at the first two lines of the error logs, it seems like for Quartus II the entities are not defined inside the qsys generated verilog file. On what could this depend?

[Altera_Forum]

Add the .qip file generated by QSYS to your project to fix this.

[Altera_Forum]

I work with Statix development kit and the Arria V starter kit. 

 I have a PCIe endpoint up but want to apter the PCIe component since the BAR sizes are set and I would liek to change them. My understanding is that the PCIe IP compiler may be required to run to generate a new PCIe component.  Can anyone give instructions on how to do this as I have not been successful to date.  Thanks, Bob

[Altera_Forum]

Hi Bob, 

  --- Quote Start ---   I have a PCIe endpoint up but want to apter the PCIe component since the BAR sizes are set and I would liek to change them. My understanding is that the PCIe IP compiler may be required to run to generate a new PCIe component.  Can anyone give instructions on how to do this as I have not been successful to date.   --- Quote End ---   Have you tried using the PCIe compiler GUI, and reading the PCIe Megacore Users Guide? The guide has screen shots and explains what the settings are. It sounds like all you want to do is to start the GUI, and edit the existing design to change the BAR sizes. If so, why? BAR sizes are usual set small, since you only ever use them to write to control registers. If you want to access anything like memory, then you should be using a DMA controller (its a lot faster for data transfer).  If you look at the PDF in the thread linked to above, it explains the settings in the PCIe GUI. It should be similar for your board.  Cheers, Dave

[Altera_Forum]

Direct access can be useful for downloading nios code and general debug. 

But unless you can get the host cpu to use dma it will be terribly slow (and you'll have difficulty getting an x86 cpu to do dma). So it does depend on how much data you need to transfer.

[Altera_Forum]

--- Quote Start ---  Hi Bob,  Have you tried using the PCIe compiler GUI, and reading the PCIe Megacore Users Guide? The guide has screen shots and explains what the settings are. It sounds like all you want to do is to start the GUI, and edit the existing design to change the BAR sizes. If so, why? BAR sizes are usual set small, since you only ever use them to write to control registers. If you want to access anything like memory, then you should be using a DMA controller (its a lot faster for data transfer).  If you look at the PDF in the thread linked to above, it explains the settings in the PCIe GUI. It should be similar for your board.  Cheers, Dave  --- Quote End ---    Dave, I still struggle with this .. the screen shot attached indicates that the Arria V isn't supported by the PCIe compiler ... I tried going through the compiler and megacore info. I am using the Avalon-MM Arria V Hard IP for PCI experess and it works but doesn't let me change the BAR sizes. ... So I have been modifying the  synthesize verilog manually where the core is instantiated. This is a problem when I come to run Modelsim since whatever Modelsim is compiling for its simulation models doesn't seem to pick up my manual changes.  I have tried to change the attribute of the .tcl file which says if the file function can is "editable" but that doesn't seem to do anything.  Any ideas on this ... or can you say which simulation file I would edit to keep the synthesize file edits in synch with the Modelsim simulation ?  Thanks, Bob

[Altera_Forum]

In Qsys, the BAR size is not editable. The BAR size will be assigned automatically when a Slave component was connected to the BAR master.