Decision scheme

[Altera_Forum]

Hi ,  

I design decision scheme in order to determine whether the signal i '0' or '1' from group of 4 bits and then the output signal of the scheme change respectively . for some reason the output signal Des_out is persistently '0' . The VHDL code is :   --process - decision scheme '0' or '1'   process (ResetP) variable score : integer range 1 to 4;  begin  score := 1 ;  if ( resetP = '1' ) then   Des_out <='0';  elsif ( clk_100M'event and clk_100M='1' ) then   for ind in 0 to 3 loop  if hlp(ind)='1' then  score := score + 1;  end if ;  end loop ;  if (score > 2) then  Des_out <= '1';  else   Des_out <= '0';  end if ;  end if ; end process;  what is wrong in the design ?why does Des_out is consistently '0' ?  does the design have to be depend in the clock event or it will change for every change in the group of 4 bits ?  how can i watch at variable score and ind during the simulation ?  Visio file attached - look at Desicion scheme (the rest is at other process) .  wave photo attached - Des_out = '0'

[Altera_Forum]

Hi odedidush again. 

 ¿Des_out goes '1' when at least one input is active? I suggest you put the decision code outside if(clk'event and... branch.

[Altera_Forum]

no , Des_out goes '1' when the majority at group of 4 bits is '1' ,  

F.E :  0000 - Des_out ='0' 0010 - Des_out ='0' 0110 - Des_out ='0' 0111 - Des_out ='1' 1111 - Des_out ='1'

[Altera_Forum]

A majority circuit. Ok. Write another process without any clock.

[Altera_Forum]

i wrote with and without clock and Des_out is consistently '0' ...

[Altera_Forum]

Please post the code.

[Altera_Forum]

are you having problems in simulation or on the real chip? have you got a testbench? does the RTL diagram look like you expected (Im a bit worried the for loop wont be making the logic you want).

[Altera_Forum]

Hi, i have problems in the Model Sim simulator ; i didn't burn it on the chip yet . 

i don't use quartos to weite the code , i write at notepad ++ so i don't synthesize it and see RTL diagram .  the code without clock : ------------------------------------------------- process (ResetP) variable score : integer range 1 to 4; begin score := 1 ; if ( resetP = '1' ) then  Des_out <='0'; else if (reserP ='0' ) then  for ind in 0 to 3 loop if hlp(ind)='1' then score := score + 1; end if ; end loop ; if (score > 2) then Des_out <= '1'; else  Des_out <= '0'; end if ; end if ; end process;  -----------------------------------------  do i need to write it differently ? without for statement ?

[Altera_Forum]

please post the whole coide, and the waveform, and the testbench

[Altera_Forum]

i attach the all project files include Test Bench . 

 First Part of files ->

[Altera_Forum]

Second Part of files ->

[Altera_Forum]

It takes time to see the whole code but I insist on majority circuit is a combinational one. An alternative vhdl is: 

 Des_Out <= '0' when ( hlp = "0000" ) else  '0' when ( hlp = "0001" ) else  '0' when ( hlp = "0010" ) else  '0' when ( hlp = "0011" ) else  '0' when ( hlp = "0101" ) else  '0' when ( hlp = "0110" ) else  '1' when ( hlp = "0111" ) else ....  You don't need any process nor variables. It's a brute force method but it works. It's the copy of the truth table of majority circuit on the code.

[Altera_Forum]

I post a code with variables and a pure combinational majority circuit. The testbench shows "test_dataout" goes high after few clocks.

[Altera_Forum]

--- Quote Start ---  I post a code with variables and a pure combinational majority circuit. The testbench shows "test_dataout" goes high after few clocks.  --- Quote End ---     thanks bertulus , you help me a lot .