connect Altera FPGA to ADC with serial LVDS interface

[Altera_Forum]

Is there an app note on how to connect Altera FPGA (preferably Stratrix IV or V) to ADCs with high-speed serial LVDS interface (e.g. Analog device AD9637)? 

I'm quite new to high speed ADCs and DACs, so I'm not familiar with how these devices are connected to Altera FPGAs. I'm looking for app note, guidelines, examples, of how to interface them.  Would also love to see a similar app note or example on connecting ADCs to Altera FPGA via JESD204 interface as well.  Thank you!

[Altera_Forum]

--- Quote Start ---  Is there an app note on how to connect Altera FPGA (preferably Stratrix IV or V) to ADCs with high-speed serial LVDS interface (e.g. Analog device AD9637)?   --- Quote End ---   Ask Analog Devices. They might have an app note for a similar part.  If there is no app note, its only because every ADC and DAC is slightly different. In the case of this part, each ADC channel is serialized and sent over LVDS.  Here's a different ADC that uses 500Mbps or 1000Mbps LVDS outputs. You can read about some of the different settings I had to consider using:  http://www.ovro.caltech.edu/~dwh/carma_board/  http://www.ovro.caltech.edu/~dwh/carma_board/at84ad001b_tests.pdf http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf  Your ADC can be configured to generate a PRBS output. You can capture that inside your FPGA to check that the data link works correctly. Take a look at this tutorial:  http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip    --- Quote Start ---   I'm quite new to high speed ADCs and DACs, so I'm not familiar with how these devices are connected to Altera FPGAs. I'm looking for app note, guidelines, examples, of how to interface them.  Would also love to see a similar app note or example on connecting ADCs to Altera FPGA via JESD204 interface as well.   --- Quote End ---    JESD204 devices use transceivers, these are different again than LVDS receivers. Here's a good overview  http://electronicdesign.com/analog/pair-right-jesd204b-converter-your-fpga  If you want to interface either of these devices to an FPGA, the first thing you need to do is get a simulation working. Learn how to use Modelsim. Create a design where your ADC is "faked" out using an LVDS transmitter, and then capture the data in your FPGA receiver logic. Use the PRBS code in the tutorial above to create the fake ADC data.  Read this tutorial too:  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf  Cheers, Dave

[Altera_Forum]

Thank you Dave. I will also check out Analog Devices app notes. 

I am hoping for more of a step-by-step instruction of how to connect the ADC to the FPGA [for both serial LVDS and JESD204B]: (1) Which Megacore function/IP to use, (2) How to set it up, (3) How/good ways to synchronize data across multiple channels of multiple ADCs , ... Xilinx has this app note that is quite helpful. I hope Altera has a similar app note. http://www.xilinx.com/support/documentation/application_notes/xapp1071_v6_adc_dac_lvds.pdf

[Altera_Forum]

On this same subject, is there a way to interface a 12 bit resolution ADC with serial-LVDS output to an Altera FPGA? Altera FPGA SERDES, however, can only deseriallize up to 10 bits. (page 20 of http://www.altera.com/literature/ug/ug_altlvds.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=altlvds_tx megafunction)

[Altera_Forum]

Did you manage to finish this ?

[Altera_Forum]

--- Quote Start ---  On this same subject, is there a way to interface a 12 bit resolution ADC with serial-LVDS output to an Altera FPGA? Altera FPGA SERDES, however, can only deseriallize up to 10 bits. (page 20 of http://www.altera.com/literature/ug/ug_altlvds.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=altlvds_tx megafunction)  --- Quote End ---    There are two way to resolve your question: 1. split 12-bit to two 6-bit; 2. use ddio + shift-register structrue