Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20693 Discussions

[Qsys]: Timing violation on reset controller

Altera_Forum
Honored Contributor II
982 Views

Hi all, 

 

I've found an timing-violation issue related to recovery timing on my Qsys system which I'm not really know what happen. 

Do you guys have any idea? 

I attach the picture for reference, thanks! 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=7934  

https://www.alteraforum.com/forum/attachment.php?attachmentid=7935
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
296 Views

Hello Grein, 

 

we have the same problem together with Quartus 13.0SP1 and NiosII/s. 

 

The following configuration did not show the recovery issue: 

- Quartus 13.0 and NiosII/s 

- Quartus 13.0SP1 and NiosII/e 

 

We assume that the hardware divide feature in the NiosII Core causes the recovery issue. 

Compared to NiosII/s, NiosII/e does not come with hardware divide. 

 

Which Quartus version and NiosII Core do you use? 

 

Regards, 

Jens
0 Kudos
Altera_Forum
Honored Contributor II
296 Views

I met the same problem. I think we can just ignore it.

0 Kudos
Reply