Amazing problem with a variable

[Altera_Forum]

Hello, 

I have a problem in my software program. My goal is to put the following signal s_nb_deph to X"FF" Here is an ectract of the software:  ELSIF RISING_EDGE(clk) then  IF (En_enteteRX ='1' AND v_tempo_En_enteteRX ='0')AND v_en_finmesurereflecto ='0' THEN  v_attente_nbdeph :='1';   ELSIF v_attente_nbdeph = '1' THEN v_cptdeph := "000001";  ELSIF v_cptdeph = "000001" AND v_cptdeph <= En_enteteRX_nbdeph THEN v_nb_deph <= X"01"; v_attente_nbdeph := '0'; v_flag_nbdeph :='1';    ELSE v_flag_nbdeph := '0'; v_en_finmesurereflecto :='0'; v_attente_nbdeph := '0'; v_en_actmoyennage:= '0'; v_nb_deph <= X"FF"; --HERE MY PROBLEM, this value doesnt' change to FF.....only X"03"  END IF;   --temporisations v_tempo_flag_moyennagetermine := flag_moyennagetermine; v_tempo_En_enteteRX := En_enteteRX ;  ELSIF FALLING_EDGE(clk) then  cpt_deph <= v_cptdeph; nb_deph <= v_nb_deph; -- So this output is not updated to the right value flag_nbdeph <= v_flag_nbdeph ; en_finmesurereflecto <= v_en_finmesurereflecto; en_actmoyennage <= v_en_actmoyennage;  END IF; END PROCESS;  I declared in entity all the input and output, in the begining of the process all the variables.  I have tried to change variable by signal (as you can see in the sreenshot attached...)   But when I do the simulation on ModelSim Altera,the signal v_nb_deph (or s_nb_deph) goes to x"00" to X"03 and then to X"01". It seems like if the 2 bits on 8 are activated. I don't know what is the problem. In my project I use Quartus 2 Can somebody tell what's the problem.

[Altera_Forum]

Right, lets start off with the first problem - this is not software, and this is not a program. VHDL is a hardware description language - so if you try and think like software, you're probably going to have trouble. Given you're using variables everywhere, I assume you come from a software background. 

 I bet the easiest fix to this will be use signals instead of variables, and before that it would probably help more if you step back and draw the circuit you're trying to design on a peice of paper (its a hardware DESCRIPTION language after all - if you dont know what the circuit should be, how do you expect to describe it?). There is almost no code that needs variables rather than signals, so as a beginner, you're better off using signals.   So next question - where is the testbench?

[Altera_Forum]

Hi ! 

 i have joined a sreenchot...  I have tried both solution : variable and signal...but same result.  why my variable v_nb_deph can't be at the value FF ??  I

[Altera_Forum]

please post the whole code and the testbench.

[Altera_Forum]

Here is the whole code: 

 library ieee; use ieee.std_logic_1164.all;  use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;    entity compteur_moyen_deph is     port(  -- Input  clk : in std_logic;  arazb : in std_logic;  En_enteteRX : in std_logic;  En_enteteRX_nbdeph : in std_logic_vector(7 downto 0);  flag_moyennagetermine : in std_logic;    -- Output  cpt_deph : out std_logic_vector(5 downto 0):= (others => '0');   nb_deph : out std_logic_vector(7 downto 0):= (others => '0');   flag_nbdeph : out std_logic :='0';  en_finmesurereflecto : out std_logic :='0';  en_actmoyennage : out std_logic :='0'  );  END compteur_moyen_deph;  ARCHITECTURE ar_compteur_moyen_deph OF compteur_moyen_deph IS      BEGIN    PROCESS(clk,arazb) IS    variable v_tempo_En_enteteRX : std_logic :='0';  variable v_tempo_flag_moyennagetermine : std_logic :='0';  variable v_attente : std_logic :='0';  variable v_reset_flag_nbdeph : std_logic :='0';  variable v_flag_nbdeph : std_logic :='0';  variable v_nb_deph : std_logic_vector (7 downto 0):= (others => '0');  variable v_cptdeph : std_logic_vector (5 downto 0):= (others => '0');   variable v_en_finmesurereflecto : std_logic :='0';  variable v_en_actmoyennage : std_logic :='0';  BEGIN    --reset  IF arazb ='0' THEN       --variables  v_tempo_En_enteteRX :='0';  v_tempo_flag_moyennagetermine :='0';  v_attente :='0'; -- modif: v_attente := '1'  v_reset_flag_nbdeph :='0';  v_flag_nbdeph :='0';  v_nb_deph := (others => '0');  v_cptdeph := (others => '0') ;   v_en_finmesurereflecto :='0';  v_en_actmoyennage :='0';    --output  cpt_deph <= (others => '0') ;   nb_deph <= (others => '0');   flag_nbdeph <='0';  en_finmesurereflecto <='0';  en_actmoyennage <='0';    ELSIF RISING_EDGE(clk) then      IF (En_enteteRX ='1' AND v_tempo_En_enteteRX ='0')AND v_en_finmesurereflecto ='0' THEN   v_attente_nbdeph :='1';    ELSIF v_attente_nbdeph = '1' THEN  v_cptdeph := "000001";   ELSIF v_cptdeph = "000001" AND v_cptdeph <= En_enteteRX_nbdeph THEN  v_nb_deph <= X"01";  v_attente_nbdeph := '0';  v_flag_nbdeph :='1';     ELSE  v_flag_nbdeph := '0';  v_en_finmesurereflecto :='0';  v_attente_nbdeph := '0';  v_en_actmoyennage:= '0';  v_nb_deph <= X"FF"; --HERE MY PROBLEM, this value doesnt' change to FF.....only X"03"   END IF;    v_tempo_flag_moyennagetermine := flag_moyennagetermine;  v_tempo_En_enteteRX := En_enteteRX ;   ELSIF FALLING_EDGE(clk) then   cpt_deph <= v_cptdeph;  nb_deph <= v_nb_deph; -- So this output is not updated to the right value  flag_nbdeph <= v_flag_nbdeph ;  en_finmesurereflecto <= v_en_finmesurereflecto;  en_actmoyennage <= v_en_actmoyennage;  END IF; END PROCESS    END ar_compteur_moyen_deph;   And here is the testbench which as been done with Modelsim-altera 6.6d:

[Altera_Forum]

thats not a testbench, thats just a waveform. Where is the testbench code?

[Altera_Forum]

ok. First problem. You cannot use both the rising and falling edges of the clock in an FPGA (it will work find in simulation, but is not possible on real hardware). For a double rate you need a 2x clock. 

Next: your waveform doesnt show many signals, and doesnt show any of the variables. How can you debug it without seeing all the input values and all the signals/variables in the if statements?  Finally: Why are you using variables at all? do you know the difference in behaviour between signals and variables? do you know what hardware they will map to? I suspect you're a software guy.  There is almost never a need a use variables. So, I suggest taking a step back, and drawing (yes, with a pen and paper) the circuit you are trying to acheive. This is a description language. without knowing what you're describing, you have no chance of writing correct code.

[Altera_Forum]

Ok, by testbench code do you mean a TCL script 

Here is the Testbench code:  restart -f  set dureetest 10000   I'll try to change the code without using rising and falling edges. force -deposit sim:/testbatch3pllstatemcompteur/\\compteur_moyen_deph|s_nb_deph\\ 00000000 0 force -deposit sim:/testbatch3pllstatemcompteur/\\compteur_moyen_deph|nb_deph\\ 00000000 0   force str_CLK_in1 0 0, 1 5ns -r 10ns  force str_arazb 1 0  force str_En_enteteRx 0 0, 1 90ns  force str_EnteteRx_NbDephase 00110000 0   force str_out_flag_finmoyennage 0 0, 1 140ns -r 150ns   view wave  run [expr $dureetest]us   I'll try to change the code without using rising and falling edges and run a simulation.

[Altera_Forum]

Using TCL forcing is not a great way to create a testbench - you're much better off writing your testbench in vhdl as you get far more control