Using M9K as shift register on a Cyclone IV

[Altera_Forum]

Hello, i have something like this: 

if sync = '1' then freq_vector(31) <= freq_in; for i in 0 to 30 loop freq_vector(i) <= freq_vector(i+1); end loop; end if; and i would to use a m9k for this shift register functionality, how can i do it?

[Altera_Forum]

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf 

 See page 14-40 and Example 14-34 on page 14-42  Or if you want to be explicit, you could use MegaWizard to create an altshift_taps

[Altera_Forum]

Thanks, exactly what i was looking for.

[Altera_Forum]

If freq_vector is 1-bit wide(i.e. it's a shift-register where the data width is 1, and only uses 32 bits), then you might need to manually force it. But if it's wide, there's a good chance synthesis will automotically put it into altshift_taps. I've seen all sorts of coding styles, but as long as you end up with a chain of registers, it can usually find it and convert it. Just make sure you don't have a reset on it, since altshift_taps can't do this.

[Altera_Forum]

It will also, by default, merge this shift register with any others it deems to be shifting in parrallel to it (same control signals) this usually wont be a problem, but on a design with tight timing requirements, having apparent timing paths between two unrelated blocks at other ends of the chip can be problematic. 

 Luckily, you can turn off shift register recognition at the block level (but its a bit more involved)

[Altera_Forum]

Through assignments it's not too difficult. Right-click on the hierarchy, Locate -> Assignment Editor, copy the name from the top into the To column of a new assignment, Auto-Shift Register Recognition = Off. 

There's also a solution for the problem you mention Tricky. (Often it was nice that synthesis did this, but when it hurt timing it was something that was very difficult for users to understand what was occuring and why.) In Quartus Assignments -> Settings -> Analysis & Synthesis is an option called Auto Shift-Register Merging Across Hierarchies. Just turn it Off. (It's set to Auto, which I believe means it follows your overall synthesis effort, i.e. Speed will not merge, Area will merge, and Balanced does one or the other but I'm not sure.)

[Altera_Forum]

--- Quote Start ---  If freq_vector is 1-bit wide(i.e. it's a shift-register where the data width is 1, and only uses 32 bits), then you might need to manually force it. But if it's wide, there's a good chance synthesis will automotically put it into altshift_taps. I've seen all sorts of coding styles, but as long as you end up with a chain of registers, it can usually find it and convert it. Just make sure you don't have a reset on it, since altshift_taps can't do this.  --- Quote End ---    Each position of the freq_vector is a 32 bits wide value :), i tried to use the ALT_SHIFT function in Megawizard but it would need 114 M9Ks to do this shift register  freq_vector((32*16)-1) <= freq_in;  for i in 0 to ((32*16)-2) loop  freq_vector(i) <= freq_vector(i+1);  end loop; With 32*16-1 taps and 32 bits wide.... Is this right?:(

[Altera_Forum]

It says it needs to have equally spaced taps that are at least three registers apart, what does it mean?

[Altera_Forum]

That's if you're tapping multiple points along the line. (I think that was the original altshift_taps function, such as tapping every few cycles in the shift register to feed a filter or something like that). You have one tap that is 32*16 long, so you easily surpass the 3 limit. What you're doing is 512 bits long, so you should get 16 bits wide in an M9K, so it should take two of them to get 32 bits wide.

[Altera_Forum]

--- Quote Start ---  That's if you're tapping multiple points along the line. (I think that was the original altshift_taps function, such as tapping every few cycles in the shift register to feed a filter or something like that). You have one tap that is 32*16 long, so you easily surpass the 3 limit. What you're doing is 512 bits long, so you should get 16 bits wide in an M9K, so it should take two of them to get 32 bits wide.  --- Quote End ---   Actually each of my taps have 32 bits and i have 32 * 16 taps, right?  [tap 0] [tap 1] [tap 2] [tap 3] [tap ..] [tap 32*16]  Each clock pulse it slides

[Altera_Forum]

Think about how the shift register is implemented in an M9K block. 

No data is moved, the addresses of the memory locations change instead. In it simplest form this means that you can only see two delayed values (there are 2 read ports). More read ports can only be generated by chaining or replicating the shift register.

[Altera_Forum]

--- Quote Start ---  Think about how the shift register is implemented in an M9K block. No data is moved, the addresses of the memory locations change instead. In it simplest form this means that you can only see two delayed values (there are 2 read ports). More read ports can only be generated by chaining or replicating the shift register.  --- Quote End ---    That's perfect dsl but why this isn't being sinthesised as a m9k shift register? It's set to recognize shift registers in the Quartus II settings  if sync = '1' then freq_vector((5*16)-1) <= freq_in; for i in 0 to ((5*16)-2) loop freq_vector(i) <= freq_vector(i+1); end loop; end if;