Hi,
I have an Altera Cyclone V GX Development Kit and trying to get the DDR3 SDRAM working. The kit have 4x 128 Mbyte with 16-bit data bus (MT41J128M16JT-125) and 2x 128 MB with 8-bit data bus (MT41J128MBJP). I have a NIOS2 w.MMU in my system and using 125Mhz pll reference clock. Using the DDR3-1333 setting from the datasheet, I did a timequest analysis but couldn't get the timing function properly. Attached is the screen capture of data arrival and required -0.429 ns slack, and setting. To have this design operate correctly, I would need to remove the slack. I greatly appreciate if anyone had work with this kit before and know how to fix my problem.
