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TimeQuest - logic generated clocks constraining

Altera_Forum
Honored Contributor II
‎10-30-2013 06:14 PM
984 Views

Hi, 

 

I've been trying to properly constrain my design, but so far unsuccessful. 

 

My scenario:  

- custom JTAG Master unit working at 10-200 MHz (PLL) and generating a TCK of PLL_freq/2 (logic generated clock).  

- master (FPGA) operates on the rising edge, slave on the falling edge of TCK. 

- sampling in the master is done with the PLL clock only 

- TDI delay to TCK negative edge ~ 7ns (target delay) 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=7976  

 

My problem is not being able to use TCK when constraining input delays for TDI because... it's no real clock, just toggling flip-flop... 

 

Can anyone give me a clue how to solve this issue? 

 

Thanks!
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