Help with test bench error message

[Altera_Forum]

Hi, I'm new to vhdl and trying to simulate a counter from 0 to 3 using integers. The code that I used for the module is below library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Counter is Port(clk : in STD_LOGIC; Reset : in STD_LOGIC; Count : out integer; Carry : out STD_LOGIC); end Counter; architecture Behavioral of Counter is signal count_int : integer; begin process (reset, clk) begin if reset = '1' then count_int <= 0; carry <= '0'; elsif clk'event and clk = '1' then if count_int <= 2 then count_int <= count_int + 1; carry <= '0'; else - count_int <= 0; carry <= '1'; end if; end if; end process; count <= count_int; end Behavioral; The test bench that I used is below LIBRARY ieee; USE ieee.std_logic_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY TB_Counter IS END TB_Counter; ARCHITECTURE behavior OF TB_Counter IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Counter PORT( clk : IN std_logic; Reset : IN std_logic; Count : OUT integer; Carry : OUT std_logic ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal Reset : std_logic := '0'; --Outputs signal Count : integer; signal Carry : std_logic; -- Clock period definitions constant clk_period : time := 50 us; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Counter PORT MAP ( clk => clk, Reset => Reset, Count => Count, Carry => Carry ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin reset => '0'; wait for 3 ns; reset => '1'; wait for 3 ns; reset => '0'; wait; end process; END; I am using ISE Project navigator and when I try to simulate the test bench I am getting these errors ERROR:HDLCompiler:806 - "C:/Users/Alex/Desktop/VHDL/counter_03/TB_Counter.vhd" Line 88: Syntax error near "=>". ERROR:HDLCompiler:806 - "C:/Users/Alex/Desktop/VHDL/counter_03/TB_Counter.vhd" Line 90: Syntax error near "=>". ERROR:HDLCompiler:806 - "C:/Users/Alex/Desktop/VHDL/counter_03/TB_Counter.vhd" Line 92: Syntax error near "=>". WARNING:HDLCompiler:1369 - "C:/Users/Alex/Desktop/VHDL/counter_03/TB_Counter.vhd" Line 85: Possible infinite loop; process does not have a wait statement ERROR:HDLCompiler:854 - "C:/Users/Alex/Desktop/VHDL/counter_03/TB_Counter.vhd" Line 39: Unit <behavior> ignored due to previous errors. Can someone advice me on what I am doing wrong and how can I amend it, thanks in advance.

[Altera_Forum]

simple, 

reset <= '0'; (you have written reset => '0') at the end

[Altera_Forum]

Wow, I did not even realise that, thank you. 

  --- Quote Start ---  simple, reset <= '0'; (you have written reset => '0') at the end  --- Quote End ---