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Hello,
I've got some problem to use the function to_unsigned. I create a program that take two inputs from switch, convert into 7 segment display and show on it. Then i start a process in which i want to sum each input and show the result on 7 segment. but when i use the function to_unsigned on this part of code i've got an error
temp <= input1+input2;
result <=to_unsigned(integer(temp));
segmentsR <= unsigned_to_seven_segment(value =>unsigned(result), number_of_digits =>2, value_is_bcd =>false);
The error is: - formal port of parameter "SIZE" must have actual or default value So i see on the ieee library what SIZE means and i saw that after ARG is necessary to write, SIZE ....... I try to modify the code in this way
result <= to_unsigned(integer(temp, SIZE:NATURAL));
Now the error is near text ":"; expecting ")" , or "," What means? Is there anyone can explain me what is SIZE? Thanks MAT
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size is a constant number specifying the result bit length.
result <=to_unsigned(integer(temp), result'length);
should work
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--- Quote Start --- size is a constant number specifying the result bit length.
result <=to_unsigned(integer(temp), result'length);
should work --- Quote End --- unfortunately didn't work.....there is another error......"variable must be constrained"
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That error probably came from elsewhere. How about posting the full code, not just a snippet.
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--- Quote Start --- That error probably came from elsewhere. How about posting the full code, not just a snippet. --- Quote End --- ok....this is the full code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.seven_segment_pkg.all;
entity Switch7Segment is
port (
SW: in std_logic_vector(9 downto 0);
HEX0: out std_logic_vector(6 downto 0);
HEX1: out std_logic_vector(6 downto 0);
HEX2: out std_logic_vector(6 downto 0);
HEX3: out std_logic_vector(6 downto 0);
KEY: in std_logic_vector(3 downto 0);
CLOCK_50: IN STD_LOGIC
);
end entity Switch7Segment;
architecture behavior of Switch7Segment is
signal segments1: std_logic_vector(13 downto 0);
signal segments2: std_logic_vector(13 downto 0);
signal segmentsR: std_logic_vector(27 downto 0);
signal input1: integer;
signal input2: integer;
signal result: unsigned;
signal temp: integer;
begin
input1 <= to_integer(unsigned(SW(4 downto 0)));
input2 <= to_integer(unsigned(SW(9 downto 5)));
segments1 <= unsigned_to_seven_segment(value => unsigned(SW(4 downto 0)), number_of_digits => 2, value_is_bcd => false);
segments2 <= unsigned_to_seven_segment(value => unsigned(SW(9 downto 5)), number_of_digits => 2, value_is_bcd => false);
HEX1 <= segments1(13 downto 7);
HEX0 <= segments1(6 downto 0);
HEX3 <= segments2(13 downto 7);
HEX2 <= segments2(6 downto 0);
PROCESS(CLOCK_50)
BEGIN
IF (CLOCK_50' EVENT AND CLOCK_50='1' AND KEY(0)='1') THEN
temp<=input1+input2;
result<=to_unsigned(integer(temp), result'length);
segmentsR <= unsigned_to_seven_segment(value => unsigned(result), number_of_digits =>2, value_is_bcd =>false);
HEX1 <= segmentsR(13 downto 7);
HEX0 <= segmentsR(6 downto 0);
END IF;
end Process;
end;
Package
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package seven_segment_pkg is
-- Return a std_logic_vector ready for driving a number of 7-segment displays.
function unsigned_to_seven_segment(value: unsigned; number_of_digits: integer; value_is_bcd: boolean)
return std_logic_vector;
end;
package body seven_segment_pkg is
function seven_seg_from_bcd_digit(bcd_digit: std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case bcd_digit is
-- abcdefg
when x"0" => return "1000000";
when x"1" => return "1111001";
when x"2" => return "0100100";
when x"3" => return "0110000";
when x"4" => return "0011001";
when x"5" => return "0010010";
when x"6" => return "0000010";
when x"7" => return "1111000";
when x"8" => return "0000000";
when x"9" => return "0010000";
when x"a" => return "0001000";
when x"b" => return "0000011";
when x"c" => return "1000110";
when x"d" => return "0100001";
when x"e" => return "0000110";
when x"f" => return "1110001";
when others => return "0000000";
end case;
end;
-- Return a vector ready for driving a series of 7-segment displays.
function unsigned_to_seven_segment(
value: unsigned;
-- Number of 7-segment displays (determines output vector width: W = 7*N)
number_of_digits: integer;
-- When true, treat the input value as a BCD number where every 4 bits hold one
-- digit from 0 to A. When false, treat the input number as an unsigned integer.
value_is_bcd: boolean
) return std_logic_vector is
variable segments: std_logic_vector(number_of_digits*7-1 downto 0);
variable bcd_quotient: unsigned(value'range);
variable bcd_remainder: unsigned(3 downto 0);
begin
if value_is_bcd then
for i in 0 to number_of_digits-1 loop
segments(i*7+6 downto i*7) := seven_seg_from_bcd_digit(
std_logic_vector(value(i*4+3 downto i*4))
);
end loop;
else
bcd_quotient := value;
for i in 0 to number_of_digits-1 loop
bcd_remainder := resize(bcd_quotient mod 10, 4);
bcd_quotient := bcd_quotient / 10;
segments(i*7+6 downto i*7) := seven_seg_from_bcd_digit(
std_logic_vector(bcd_remainder)
);
end loop;
end if;
return segments;
end;
end;
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The problem is here:
signal result: unsigned; The unsigned type must have a range, like a std_logic_vector. NOTE: all errors will have a line associated with them, so you can check the offending code.- Mark as New
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On a side note: I hope you are not expecing to run this code at any high clock frequency (like anything above 20MHz) as it has chained mod and divide functions in a single clock.
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And you have multiple drivers on HEX0 and HEX1 outputs
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--- Quote Start --- And you have multiple drivers on HEX0 and HEX1 outputs --- Quote End --- Infact this is another problem, i will see how resolve it
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At the beginning i think that with a clock that scan process the problem of multiple driver HEX will be resolve......
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you cannot drive a signal from inside and outside of a process... so you cannt assign them from both places..
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now i understand and the code works
bye
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