timing problem with 8051 integration

[Altera_Forum]

Hi, 

 I have a serious timing problem in my design.  My design includes a 8051 CPU and a SPI protocol.   Each design on it's one, allows me a ~130Mhz frequency.  For some reason, once I integrate them, my Fmax falls down to 60Mhz. The intresting thing is that when I looked up on my critical paths, I saw it is one part of the 8051, nothing to do with the integration of the two designs.  Any advise why such thing should happen? any idea how to fix it?  Thanks in advance, David

[Altera_Forum]

I though of a "work around" solution: if after I compile my 8051 on it's own, i save the file, and then integrate the post synthesis 8051 with my SPI, it might overcome the problem. 

 Can anyone explain to me how do i do such a thing? I mean what file from the 8051 project should I take and add to the combined project (instead of the 8051.v files I added as for now), and how do i tell the Quartus to keep it's design?   i am still very happy to hear other ideas.  Tahnks again, David

[Altera_Forum]

Hard to tell. 

Maybe it's due to placement. The more you fill your FPGA, the more you start to have non-optimal routing.

[Altera_Forum]

I suppose, 

but do you know how can I do what I offered above?

[Altera_Forum]

You need a paid version of Quartus, but you can partition your design. 

This will allow you to have fixed place & route for each partition.

[Altera_Forum]

Thanks, 

 I have a paid version.   Can you reffer me to some toutorial of this partitioning tool?  couldn't find any user friendly stuff on the net.  Thanks, David.