Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Using System console for utilizing the USB debug master component in Qsys

Altera_Forum
Honored Contributor II
‎11-08-2013 05:21 AM
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Hi all I ve been working on Cyclone V soc development kit and intend to communicate through dedicated USB lines from the FPGA to the PC through the MAX II CPLD(USB Blaster II). I got recommendations to use the USB debug master in order to implement this but since i am a newbie to Tcl script and have time restrictions would like to know if there is a tcl script for testing this component with the set of commands for USB read and write. 

 

Thanks in advance, 

CG6991
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Altera_Forum
Honored Contributor II
‎11-11-2013 03:04 AM
564 Views

 

--- Quote Start ---  

Hi all I ve been working on Cyclone V soc development kit and intend to communicate through dedicated USB lines from the FPGA to the PC through the MAX II CPLD(USB Blaster II). I got recommendations to use the USB debug master in order to implement this but since i am a newbie to Tcl script and have time restrictions would like to know if there is a tcl script for testing this component with the set of commands for USB read and write. 

 

Thanks in advance, 

CG6991 

--- Quote End ---  

 

 

You can use Virtual JTAG to debug and test your fpga design. Virtual JTAG is one of Altera's megafunction, you can implement it like other free function by using megawizard.
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