No feasible entries for subprogram “CONV_INTEGER”

Altera_Forum · ‎11-09-2013

I have implemented a simple adder component with two inputs and one output.

port ( a,b : in std_logic_vector(31 downto 0);

r : out std_logic_vector(31 downto 0)

);

I created a test bench in order to test this component. Then I modified this test bench in order to read the inputs from a text file and in order to write the results to a text file. Currently inputs must be binary strings; similarly, the output is written as a binary string.

Now I would improve this test bench in order to read inputs as integer value from text file. I was able to make this change successfully. But I would also like the output to be written as an integer: in this case, the compiler reports an error on a line of the following source code.

architecture tb4 of tb4_adderbehav is

component adderbehav is

port ( a,b : in std_logic_vector(31 downto 0);

r : out std_logic_vector(31 downto 0)

);

end component;

signal a,b : std_logic_vector(31 downto 0);

signal r : std_logic_vector(31 downto 0);

begin

dut: adderbehav port map (a,b,r);

process

variable tbinputs, tboutput : line;

variable va, vb, vr : integer;

file data_file : text;

file result_file : text;

begin

file_open(data_file,"dati_int.txt",read_mode);

file_open(result_file,"risultati_int.txt",write_mode);

while not endfile(data_file) loop

readline(data_file,tbinputs); read(tbinputs,va); read(tbinputs,vb);

a <= conv_std_logic_vector(va, a'length);

b <= conv_std_logic_vector(vb, b'length);

wait for 10 ns;

--vr := conv_integer(r); -- error: no feasible entries for subprogram "conv_integer"

--write(tboutput,vr);

write(tboutput,r);

writeline(result_file,tboutput);

end loop;

file_close(data_file);

file_close(result_file);

wait;

end process;

end tb4;

Why does the error occur in the source code shown above?

In the source code I have included the following libraries:

- ieee.std_logic_1164.all;

- ieee.std_logic_textio.all;

- ieee.std_logic_arith.all;

- ieee.numeric_std.all;

- std.textio.all;

Thank you in advance for any support!

Altera_Forum · ‎11-09-2013

The problem is that you didnt include the std_logic_signed or std_logic_unsigned library (you cannot add both)

But just as a comment on the same theme - you shouldnt be using these libraries (and therefore conv_integer function) as it is not standard VHDL. You have also included both std_logic_arith and numeric_std which have conflicts, and so std_logic_arith should be removed (again, a non-standard library).

Then, to convert to an integer:

vr := to_integer( unsigned(R) );

or

vr := to_integer( signed(R) );

if you need a signed version.

The problem with std_logic_(un)signed is that you are limited to signed OR unsigned arithmatic in an entity. Numeric std defines both unsigned and signed types and therefor allows you to do both.

PS> You should remove the conv_std_logic_vector function too. Replace with:

B <= std_logic_vector( to_unsigned(vb, B'length) );

Or to minimuse on the type conversions, just use an integer on your ports. You dont have to use std_logic_vector everywhere.