Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16556 Discussions

Clock delay is too long...

Altera_Forum
Honored Contributor II
1,296 Views

hi, everyone! I have an project with major clock freq of 125Mhz, generated by register from 250Mhz clock source. Data is tranfered from 125Mhz clock domain to 250Mhz clock domain, and setup slack is about -1.2ns. I have checked that the average clock delay of 125Mhz clock is 7.x ns. Meanwhile, clock delay in 250Mhz clock demain is 3.8 ns. How can I reduce the clock delay of 125Mhz clk? Thx! :)

0 Kudos
7 Replies
Altera_Forum
Honored Contributor II
533 Views

Are you generating a clock or a clock enable from the register? If you need to generate a clock, use a PLL.

0 Kudos
Altera_Forum
Honored Contributor II
533 Views

 

--- Quote Start ---  

Are you generating a clock or a clock enable from the register? If you need to generate a clock, use a PLL. 

--- Quote End ---  

 

yes, it's generated by a register. The generation of 125M clk is a part of an IP. So, I think I'd better not to modify it...
0 Kudos
Altera_Forum
Honored Contributor II
533 Views

FPGA's have relatively long, pre-built, clock distribution trees. 

Due to that, when you generate a clock using logic, it's going to have a relatively long delay compared to the source clock. Which means using logic generated clocks tends to be a bad practice. 

 

If you can't modify the IP, I suggest you use a PLL to generate two 250 MHz clocks, with different phases. Feed one to the IP block and use the other to receive data from the 125 MHz clock. 

By choosing a suitable phase delay between the two 250 MHz clocks, you might be able to work around your problem.
0 Kudos
Altera_Forum
Honored Contributor II
533 Views

 

--- Quote Start ---  

FPGA's have relatively long, pre-built, clock distribution trees. 

Due to that, when you generate a clock using logic, it's going to have a relatively long delay compared to the source clock. Which means using logic generated clocks tends to be a bad practice. 

 

If you can't modify the IP, I suggest you use a PLL to generate two 250 MHz clocks, with different phases. Feed one to the IP block and use the other to receive data from the 125 MHz clock. 

By choosing a suitable phase delay between the two 250 MHz clocks, you might be able to work around your problem. 

--- Quote End ---  

 

 

thanks for your reply! 

Yeah, I had dallied with the idea of using the other 250Mhz clock with different phase, but I didn't take it out... I will try it, tks! 

 

0 Kudos
Altera_Forum
Honored Contributor II
533 Views

 

--- Quote Start ---  

FPGA's have relatively long, pre-built, clock distribution trees. 

Due to that, when you generate a clock using logic, it's going to have a relatively long delay compared to the source clock. Which means using logic generated clocks tends to be a bad practice. 

 

If you can't modify the IP, I suggest you use a PLL to generate two 250 MHz clocks, with different phases. Feed one to the IP block and use the other to receive data from the 125 MHz clock. 

By choosing a suitable phase delay between the two 250 MHz clocks, you might be able to work around your problem. 

--- Quote End ---  

 

 

Q1:Why the delay between output and input of the pll is an negetive value? 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8036  

Q2:I want to set the constraint of two outputs of the pll, but I can only find one clock ouput...
0 Kudos
Altera_Forum
Honored Contributor II
533 Views

In normal mode, the PLL will compensate the clocks for the delay of the clock tree. 

In other words, the PLL's output clock will be "ahead" of the input clock in such a way that, at the end of the clock tree, the PLL clock will be in phase with the input clock. 

 

derive_pll_clocks 

^^ Add this, and TimeQuest will automatically create and constrain all the PLL output clocks
0 Kudos
Altera_Forum
Honored Contributor II
533 Views

 

--- Quote Start ---  

In normal mode, the PLL will compensate the clocks for the delay of the clock tree. 

In other words, the PLL's output clock will be "ahead" of the input clock in such a way that, at the end of the clock tree, the PLL clock will be in phase with the input clock. 

 

derive_pll_clocks 

^^ Add this, and TimeQuest will automatically create and constrain all the PLL output clocks 

--- Quote End ---  

 

ok! Thank you, rbugalho, I get it!
0 Kudos
Reply