i need to contraint a input port which is registered by for clock edge(clk0 rising, clk90 rising, clk0 falling, clk90 falling).
i have done these using set_max_skew in v9.1 quartus with cyclone2 . it works well.
now i constraint it in quartus 13.0SP1 with 5CGXFC7.
the max skew counld not meet.
through the report max skew.i found two difference.
1. in 13.0SP1, for ths same path. the 'Latest Path Arrival' analyze the FF data path, and 'Earliest Path Arrival' analyze the RR data path.
so 8 paths were analyzed. but in previous version, only RR data path.4 path only.
2. the two clock both go through global network. but clock network delay are diffrent. 'Latest Path Arrival' is 1.255 and 'Earliest Path Arrival' is 2.716. i think the difference is beacuse of FF and RR to edge, seems like quarter clock period. so i add some false path but it didnt change anything.
anyone could help me?
