VHDL Module simulation

[Altera_Forum]

Hi, I'm new to VHDL and find it difficult to create a testbench for a code. The code will display A5A5 when the input is '00', it will display 12345678ABCDEF when the input is '01', display 500662 when the input is '10' and it will display 503188 '11'. I'm using ISE Project navigator which creates the test bench but I can't get the right parameters to test the code, can anyone guide me on how to proceed about this. The code is below : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DataGen is Port ( Input : in STD_LOGIC_VECTOR (1 downto 0); CLK, Reset : in STD_LOGIC; Output : out STD_LOGIC_VECTOR (15 downto 0)); end DataGen; architecture Behavioral of DataGen is signal counter : STD_LOGIC_VECTOR (1 downto 0); begin process ( Reset, CLK ) begin if Reset = '1' then -- If the reset button is pressed it clears Counter <= "00"; -- the Counter value and sets it to 00 elsif CLK'event and CLK = '1' then -- Used for Mode 1,2,3; Increments the value of Counter Counter <= counter + '1'; -- each time the CLK singal is 1 therefore creating an endless if Counter = "11" then -- loop for Counter else counter <= "00"; end if; end if; end process; process ( Input, CLK, Reset, Counter ) begin if Reset = '1' then -- Resets the 7-segment display if Reset is 1 Output <= X"0000"; elsif CLK'event and CLK = '1' then --Mode 0 if Input = "00" then --if selected it will display A5A5 Output <= X"A5A5"; --Mode 1 elsif Input = "01" then -- if selected will display 1 to F continously case Counter is when "00" => Output <= X"0123"; when "01" => Output <= X"4567"; when "10" => Output <= X"89AB"; when "11" => Output <= X"CDEF"; when others => Output <= X"0000"; end case; -- Mode 2 elsif Input = "10" then --if selected will display 500662 continously case Counter is when "00" => Output <= X"5006"; when "01" => Output <= X"6250"; when "10" => Output <= X"0662"; when "11" => Output <= X"5006"; when others => Output <=X"0000"; end case; -- Mode 3 elsif Input = "11" then --if selected will display 503188 continously case Counter is when "00" => Output <= X"5031"; when "01" => Output <= X"8850"; when "10" => Output <= X"3188"; when "11" => Output <= X"5031"; when others => Output <= X"0000"; end case; end if; end if; end process; end Behavioral; ]

[Altera_Forum]

Here you have a testbench for simulate a sychronous circuit. They have 4 process: 

 1-generates a clock. 2-generates reset. ( probably '0' active ). 3-generates a signal that you don't have. 4-generates a vector input signal. You should adapt it to your code.