[ModelSim] Passing real values to submodule

Altera_Forum · ‎11-11-2013

I am having a strange problem when I try to simulate my design. I would like to use real values for stimulus, since my design should work with double precision floats. But when I pass values from top module to submodule, they are not recognized correctly.

When I try to simulate the folowing code using ModelSim Altera Starter Edition 10.1d:


//------------------------------------------
// top module
//------------------------------------------
module realTest;
real a = 1.2345;
wire  out_wire;
// stimulus
always# 10 begin
    a <= a + 1.0;
   # 5
    $display("top module: 0x%x %f", out_wire, a);
end
// submodule instantiation
submodule submodule_inst (
    .data    (a),
    .out    (out_wire)
);
endmodule
//------------------------------------------
// submodule
//------------------------------------------
module submodule(
    input  data,
    output  out
);
// temporary value
real tmp;
always @ * begin
    tmp <= data;    // I THINK THE PROBLEM HAPPENS HERE
    $display("inside submodule: 0x%x %f", data, tmp);
end
assign out = data;
endmodule

I get folowing result:

#  inside submodule: 0x3ff3c083126e978d 0.000000#  inside submodule: 0x3ff3c083126e978d 4608238512912635900.000000#  inside submodule: 0x4001e04189374bc6 4608238512912635900.000000#  inside submodule: 0x4001e04189374bc6 4612214065483697200.000000#  top module: 0x4001e04189374bc6 2.234500#  inside submodule: 0x4009e04189374bc6 4612214065483697200.000000#  inside submodule: 0x4009e04189374bc6 4614465865297382400.000000#  top module: 0x4009e04189374bc6 3.234500#  inside submodule: 0x4010f020c49ba5e3 4614465865297382400.000000#  inside submodule: 0x4010f020c49ba5e3 4616453641582912500.000000#  top module: 0x4010f020c49ba5e3 4.234500

We can see that hexadecimal values are always the same, problem happens in line where hex is converted to real.

Does anybody have any idea what is wrong?

Best regards,

Jan

Altera_Forum · ‎11-11-2013

This looks like a ModelSim bug, although you probably do not want the code written this way anyways. Your real value would be converted to an integer and you would lose precision. You probably meant.

// submodule instantiation
submodule submodule_inst (
    .data    ($realtobits(a)), // IEEE 754 representation of a double precision floating point number.
    .out    (out_wire)
);
always @ * begin
    tmp <= $bitstoreal(data);  
end

Note that you can use SystemVerilog to pass a real through a port with the module declaration

module submodule(
    input real data,
    output real out
);

But at some point, you need to convert the real value into a bit representation recognized by your design.

Altera_Forum · ‎11-12-2013

Yes, declaring explicit conversion ( $realtobits() ) solves problem. Thanks.