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What are the multi cycle constraints reference launch and latch edges

Altera_Forum
Honored Contributor II
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Hello, 

 

can anybody tell me what the default launch and latch edges for multi cycle constraints are? 

 

Here is a timing diagram which I use to visualize the start/end setup/hold relationships for multi cycle constraints: 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8094  

 

The clock constraints for this example could look like this: 

set_time_format -unit ns -decimal_places 3 set t_period_50mhz 20.000 set t_period_100mhz 10.000 create_clock -name clk_50mhz -period ${t_period_50mhz} create_clock -name clk_100mhz -period ${t_period_100mhz} -waveform {5 10}  

 

In this example the first launch edge would be at t0 (rising edge to rising edge transfers) and the first latch edge would be at t0 + 5 ns. 

 

How are the default setup and hold relationships determined? 

 

Can I assume for the setup relationship the following?: 

  • Default launch edge = the first launch edge which comes after >= t0 (in this case the first launch edge would be at t0)  

  • Default latch edge = the first latch edge which comes after the first launch edge, in this case > t0  

 

 

Now for the hold relationship: 

  • Default launch edge = second launch edge which comes after >= t0 (in this case the second launch edge would be at t0 + t_period_50mhz)  

  • Default latch edge = first latch edge which comes at the same time or just before the second launch edge (the second hold launch edge in this example is at t0 + t_period_50mhz and the nearest latch edge before or equal would be at t0 + 1.5 * t_period_100mhz)  

 

 

Regards 

Martin
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Altera_Forum
Honored Contributor II
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default launch edge is just any edge. Timequest does not check every edge in a dynamic way but it is static analysis so it looks at a path and views any edge of source register clock as a launch. 

 

for setup check, latching edge is then the first edge at destination register following the launch edge at source register as you mentioned(for this edge definition the final delays inserted are zeroed but come in action at timing report). 

 

for hold check, again your are right, it is the nearest edge at destination register before the launch at source register.(again assuming delays of zero)
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Altera_Forum
Honored Contributor II
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Thanks for your input so far! As to the best of my knowledge I've tried to write down all the information in the Wiki:multicycles timing constraints (http://www.alterawiki.com/wiki/timing_constraints#multicycles). If you think there's anything missing or wrong it would be nice if you contributed!

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