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Strange simulation results

Altera_Forum
Honored Contributor II
989 Views

Hi, 

 

I've been playing around with my models behavior to try and combine it into one process. However when I simulate it I am getting some odd results. Iv'e attached a jpeg of the testbench results. 

 

1. The simulation does not work for the 1st clock cycle. 

2. At time 24 ns, outputs a and f show '1'. This is during count 5, where the code states they should be at '0'. 

3. At time 50 ns, reset is '1' - this should hold the process at count 0 (only c and d are '1'). However it does not happen. 

 

Could anyone shed some light onto this for me? Code is: 

 

entity seq2 is 

port (clk : in std_logic; 

enable : in std_logic; 

reset : in std_logic; 

a,b,c,d,e,f : out std_logic); 

end seq2; 

 

 

architecture behaviour of seq2 is 

 

signal count : integer range 0 to 5;  

signal vector : std_logic_vector (5 downto 0); 

 

begin 

 

process(clk, enable, reset)  

begin 

if reset = '1' then 

count <= 0; 

elsif falling_edge (clk) then 

if enable = '1' then 

if count < 5 then 

count <= count + 1; 

case count is 

when 0 => vector <= "001100";  

when 1 | 5 => vector <= "011110"; 

when 2 | 4 => vector <= "110011"; 

when 3 => vector <= "100001"; 

end case; 

else count <= 0; 

end if; 

end if; 

end if; 

end process; 

 

 

a <= vector(5); 

b <= vector(4); 

c <= vector(3); 

d <= vector(2); 

e <= vector(1); 

f <= vector(0); 

 

 

end behaviour;
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Altera_Forum
Honored Contributor II
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I think waveform is correct. You can observe that once reset is applied to the design,you will get the expected data. As you are not applying reset at start up,count value will be undefined. You should reset the sequential logic first. You haven't added count signal.Observe the count signal.

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Altera_Forum
Honored Contributor II
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This simulation is working exactly as you coded it. I think you're forgetting that a-f are syncrhonous to the clock. And you have also not reset the vector signal, therefore the reset works like a synchrous enable for the vector signal (ie. reset = '1' means do not update vector) therefore a-f will not change.

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Altera_Forum
Honored Contributor II
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Thanks for the explainations, I understand what went wrong with the reset now. Thank you for explaining it to me guys!

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