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I've been messing around with the DE0 Nano board and then recently took my design and moved it to my own board (my first FPGA board :) ). The HDL on the DE0 nano is the same as the HDL on my board. The FPGA on the DE0 Nano is the EP4CE22F17C6 and the one on my board is the EP4CE22E22C8. Right off, the speed grade would be my guess as to the reason why all PLLs work on the DE0-N board, but not on mine, however, I checked the handbook, and I'm well within specs for both devices.
Here's the PLL settings from my spreadsheet: Primary Clock 50.0000E+6 PLL1_Multiplier1 1 PLL1_Divider1 100 PLL1_Multiplier2 5 PLL1_Divider2 102 PLL1_Multiplier3 1 PLL1_Divider3 50 PLL1_Multiplier4 5 PLL1_Divider4 51 PLL2_Multiplier1 1 PLL2_Divider1 25 PLL2_Multiplier2 10 PLL2_Divider2 51 PLL2_Multiplier3 2 PLL2_Divider3 25 PLL2_Multiplier4 20 PLL2_Divider4 51 PLL3_multiplier1 4 PLL3_divider1 1 Based on these settings, VCO on PLL1 should be 250 MHz and VCO on PLL2 should be 1GHz and VCO on PLL3 should be 200. I'd imagine that, if required, quartus automatically bumps up the multiplier and divider values to get VCO above 600 MHz. The highest output frequency is on PLL3 at 200 MHz. After that is 19.6 MHz on PLL2 (50MHz * 20 / 51). All three PLLs put out the correct frequencies on the DE0-N board, but PLL2 outputs only DC on my board (with the slower EP4CE22E22C8). Pp. 470 (table 1-25) of the C IV handbook leads me to believe that the PLLs should work on both devices. I might try populating a board with a EP4CE22E22C6 and see if that sorts things out, but naturally I'd rather use the cheaper C8 when everything I'm doing is pretty slow speed (20 MHz or slower).Link Copied
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My guess would be a wiring error on the board, or needing more analog PLL supply filtering.
Have you tried to reduce your VCO settings, to see if you can get any output? Also try to observe the PLL source clock on a output or through signal tap directly. If you have to much noise on the PLL supplies, they will have difficulties locking, or may loose lock. If you don't have the source clock, you will never lock. Pete- Mark as New
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--- Quote Start --- Have you tried to reduce your VCO settings, to see if you can get any output? --- Quote End ---
Primary Clock 50 MHz
PLL1_Multiplier1 1
PLL1_Divider1 100
PLL1_Multiplier2 1
PLL1_Divider2 25
PLL1_Multiplier3 1
PLL1_Divider3 50
PLL1_Multiplier4 2
PLL1_Divider4 25
PLL2_Multiplier1 1
PLL2_Divider1 25
PLL2_Multiplier2 4
PLL2_Divider2 25
PLL2_Multiplier3 2
PLL2_Divider3 25
PLL2_Multiplier4 8
PLL2_Divider4 25
PLL3_Multiplier1 4
PLL3_Divider1 1
With these settings, all 3 PLLs are working. However, these frequencies are not desirable for my design. --- Quote Start --- Also try to observe the PLL source clock on a output or through signal tap directly. --- Quote End --- I have a couple of test GPIO that I connect signals to for inspection. These go to probe sockets on the board for easy measurements. --- Quote Start --- If you have to much noise on the PLL supplies, they will have difficulties locking, or may loose lock. If you don't have the source clock, you will never lock. My guess would be a wiring error on the board, or needing more analog PLL supply filtering. --- Quote End --- For the most part the power and clock are similar to the DE0_Nano board. I have a single 50mhz clock (http://www.digikey.com/product-detail/en/asflmb-50.000mhz-ly-t/535-11033-1-nd/2624500) that feeds all 3 PLLs. I also use the same method for power supply filtering as what is used on the DE0Nano board: I have a 1.2V SMPS with a large range of bypass caps that go into a ferrite bead with more bypass caps which goes into the PLL supply pins. If it is the power, I could do a 1.2V SMPS for VCCINT and a 1.2V LDO for the PLL... I'll try measuring the ripple on VCC_PLL on both boards and see if that could be it.
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