Basics - 2 inputs, 1 output + positive edges

[Altera_Forum]

Quartus II, version 10.1, Cyclone II. 

 I'm newbie in Verilog. I need a block: module (input x1,x2, output reg Y);  if (positive edge of x1) Y=0; if (positive edge of x2) Y=1;  I tried "always @(posedge x2) begin zliczaj=1;  @(posedge x1) zliczaj=0; end" but i had error "multiple event control statements not supported for synthesis".  I tried "always @(posedge clear) zliczaj=1;  always @(posedge pelne) zliczaj=0;" but i had error "can't resolve multiple constant drivers for net 'Y' at ....".  How to do that?

[Altera_Forum]

--- Quote Start ---  Quartus II, version 10.1, Cyclone II.  I'm newbie in Verilog. I need a block: module (input x1,x2, output reg Y);  if (positive edge of x1) Y=0; if (positive edge of x2) Y=1;  I tried "always @(posedge x2) begin zliczaj=1;  @(posedge x1) zliczaj=0; end" but i had error "multiple event control statements not supported for synthesis".  I tried "always @(posedge clear) zliczaj=1;  always @(posedge pelne) zliczaj=0;" but i had error "can't resolve multiple constant drivers for net 'Y' at ....".  How to do that?   --- Quote End ---    you should drive Y only on one clock edge. you better have a clk faster than x1 ,x2 then use x1 as enable to drive '0' on Y and use x2 as enable to drive '1' on Y (within the same clocked process). This will drive Y on the clk edge but not on x1,x2 edges. If you mean by x1 or x2 edge its transition fron 0 to 1 sample then you add extra logic as your enable.

[Altera_Forum]

You cannot have a signal being changed by two different processes. This would be the equivalent of having two registers with different clocks having their outputs tied together. 

 Generally you would use a clock signal for doing edge triggering. The signals you then wish to trigger off would be used as enables. IE.