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EPM7128S jtag configuration... pull-ups/downs?

Altera_Forum
Honored Contributor II
‎12-20-2013 06:20 PM
1,472 Views

Hi All, 

 

The EPF10k10 fpga needs a couple of pull-ups / downs on most of the JTAG pins. Does the same hold for the EPM7128S series? I can't find a document detailing the nitty gritty... 

 

Cheers, 

 

Mux
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Altera_Forum
Honored Contributor II
‎12-21-2013 11:21 AM
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I can't find anything specific for MAX7000 parts either. However... 

 

These devices work perfectly well in JTAG chains containing Altera FPGAs which do, generally, have guidance on how to pull up/down the JTAG signals. Therefore, they must clearly operate quite happily with the same resistors. 

 

General rule off thumb: 1k pull down on TCK, 1k-10k pull up on TDI and TMS.
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Altera_Forum
Honored Contributor II
‎12-22-2013 04:10 AM
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Thanks! I've seen some pretty exotic contraptions but I figured I'd ask here first. Most of them don't use ANY pull-ups but I figured better safe than sorry :-)

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