Large 2D registers using a lot of logic!

[Altera_Forum]

Hi, 

 So I am building sort of a grid for mapping specific data using Verilog for a DE-1 board. This is the specific code.    reg [3:0] accumulator [0:100][0:100];  The simulation works perfect on Modelsim, but when compiling it on Quartus II, the compiler is building the registers using the logic. I was wondering if there is a way I could make it use the memory in the board or some other way I can build a 2D array map using the memory. Thanks for any suggestion in advance.

[Altera_Forum]

Quartus will synthesize the registers in internal RAM, if the design structure corresponds to the RAM inference scheme shown in the Quartus software manual and in the language templates.  

 The main restrictions are required synchronous operation and that only one memory location can be accessed for a clock cycle (respectively two for a dual-port RAM). It should be noted, that Quartus showa only limited intelligency in RAM inference and probably doesn't recognize equivalent structures that objectively allow RAM inference. E.g. 2D-addresses aren't accepted, you have to map it to 1D manually.

[Altera_Forum]

--- Quote Start ---  Hi,  So I am building sort of a grid for mapping specific data using Verilog for a DE-1 board. This is the specific code.    reg [3:0] accumulator [0:100][0:100];  The simulation works perfect on Modelsim, but when compiling it on Quartus II, the compiler is building the registers using the logic. I was wondering if there is a way I could make it use the memory in the board or some other way I can build a 2D array map using the memory. Thanks for any suggestion in advance.  --- Quote End ---   I think you can implement same design by using 16 LUTs.

[Altera_Forum]

--- Quote Start ---  I think you can implement same design by using 16 LUTs.  --- Quote End ---    How? When I use it as is, Quartus II uses around 80% of the logic elements for cyclone II, without it's just 5%.

[Altera_Forum]

--- Quote Start ---  Quartus will synthesize the registers in internal RAM, if the design structure corresponds to the RAM inference scheme shown in the Quartus software manual and in the language templates.   The main restrictions are required synchronous operation and that only one memory location can be accessed for a clock cycle (respectively two for a dual-port RAM). It should be noted, that Quartus showa only limited intelligency in RAM inference and probably doesn't recognize equivalent structures that objectively allow RAM inference. E.g. 2D-addresses aren't accepted, you have to map it to 1D manually.  --- Quote End ---    In that case I will have convert the 2 coordinate addresses into 1 and back to 2 when I want to output? I am basically trying to design a 2D grid, do you know of any better way apart from using one huge RAM block?

[Altera_Forum]

--- Quote Start ---  In that case I will have convert the 2 coordinate addresses into 1 and back to 2 when I want to output?  --- Quote End ---   Why back to 2? You simply concatenate both address vectors to one when assigning the RAM address.

[Altera_Forum]

--- Quote Start ---  Why back to 2? You simply concatenate both address vectors to one when assigning the RAM address.  --- Quote End ---     Because in the end, I will traverse through the ram and determine cells with some specific value and require the 2D addresses of those cells.

[Altera_Forum]

You can also use the "MegaWizard Plug-In Manager" (under Tools menu) in Quartus to generate a RAM block and say it must be in the ram cells of the FPGA. That will use the altera optimized memory compiler, which may be better.