Complete tool for beginners

[Altera_Forum]

Hi, i just started learning about VHDL and FPGAs. I have found too many information online and i don't know where to start from. I am wondering if Quartus Web edition and ModelSim is everything i need in order to start programming in VHDL and see results. I don't own a board at the moment so everything will be done in simulation.

[Altera_Forum]

Yes, Modelsim and Quartus are sufficient in terms of software.  

 Do you have a VHDL book to learn from?  While writing code, you need to keep in mind that there are VHDL constructs destined for synthesis (by Quartus), and others used only during simulation (in Modelsim). Your VHDL book should talk about this.  The Quartus text editor has a set of templates; create a new text file, right-click in the body of the text window, and click on insert template. Look at those templates, fill in the details, and then try synthesizing the code.  Once you write VHDL that is more complex than simply blinking an LED, you should create a testbench, i.e., a fake environment in which to test the component that you will synthesize.  Try and write some code, study whatever VHDL books you have, and when you get stumped, ask questions on this list.   Please do not waste our time asking trivial questions that your books answer. When you ask questions, if you can show that you have put some effort into trying to figure it out yourself, then you will get more answers from the readers of this forum.  Cheers, Dave

[Altera_Forum]

I own circuit design with vhdl by volnei a. pedroni (http://www.amazon.com/circuit-design-vhdl-volnei-pedroni/dp/0262162245) it seems to be enough for a start.  

   --- Quote Start ---  Once you write VHDL that is more complex than simply blinking an LED, you should create a testbench, i.e., a fake environment in which to test the component that you will synthesize.   --- Quote End ---    What do you mean by that? Can i do it using quartus II?

[Altera_Forum]

A testbench is a VHDL entity you usualy do not intend to synthesise. It will create stimulus for the unit under test, and hence will probably have things that are not suitable for synthesis: 

 eg:  --clock generator clk <= not clk after 10 ns; --50MHz clock.

[Altera_Forum]

I had a bit of difficult time understanding in the beginning too. I keep posting on my blog the different design steps I follow (as I learn). Hope the blog posts help.  

http://techiesurabhi.blogspot.ca/