DE2-115 SRAM Avalon Wrapper Problem

[Altera_Forum]

Hello, 

 I am using the DE2-115 board with 50 MHz clock coming from Y2 pin. I have written a Avalon Wrapper in VHDL for interfacing the SRAM chip (IS61WV102416BLL-10) and then set the timing parameters using the SOPC tool. However when I do a memory test on the SRAM in NIOS2 EDS, the reads are different from the writes. I can not communicate with the SRAM in a healthy fashion. I suspect that the timing parameters could be wrong. Has anyone been successful in implementing and testing their own SRAM controller to control the DE2-115's SRAM?   Thanks in advance

[Altera_Forum]

Ok after a vast amount of headaches I figured that the code above works perfectly fine when I am using the address width of 18 bits. Hence I can access 512 KB of the SRAM which is sufficient for my application. However it would still be nice to know why I can't use the whole SRAM since it is 2 MB. I checked the SRAM chip's functionality by writing and reading images from the control panel. There is no problem with that. Any ideas?