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Hi, I'm developing a communication system emulator for educational purpose (university project). Now I'm blocked with the Interleaver and Deinterleaver modules I have written using Verilog. I implemented a convolutional block interleaving scheme with 8bit symbol length and 32 branches. The RTL description is composed by a bank of shift registers, a mux and a counter to control the enable bus and mux. Simulating the design (Interleaver followed by the Deinterleaver) I get a strange behaviour: data are roughly recovered but the 8th bit of every symbol is always zero and the 7th is not correct. I thought it was something related with the counter synchronization, but it seems not. Any idea? I post the code here, maybe it can be also helpful for someone else.
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/*Interleaver followed by Deinterleaver*/
module test_interleaver(
input data_in,
input valid_in,res,clk,
output reg deinterleaver_out,
output de_valid_out,
output reg counter //for debug purpose
);
integer i;
reg clk_en;
wire valid_out;
reg data_out;
assign valid_out=valid_in;
/*Interleaver branches*/
reg D1;
reg D2 ;
reg D3 ;
reg D4 ;
reg D5 ;
reg D6 ;
reg D7 ;
reg D8 ;
reg D9 ;
reg D10;
reg D11;
reg D12;
reg D13;
reg D14;
reg D15;
reg D16;
reg D17;
reg D18;
reg D19;
reg D20;
reg D21;
reg D22;
reg D23;
reg D24;
reg D25;
reg D26;
reg D27;
reg D28;
reg D29;
reg D30;
reg D31;
reg D32;
wire branch_in ;
reg branch_out;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
assign branch_in = data_in;
/*counter*/
always@(posedge clk or posedge res)
begin
if(res)counter<=5'd0;
else//clk
begin
if(valid_in)counter<=counter+5'd1;
else counter<=counter; //hold
end
end
/*switch and enable control (these 2 modules are tested and work properly)*/
mux_8x32 switch_int(.counter(counter),.branch_out(branch_out), .data_out(data_out));
enable_coder en_bus_int(.counter(counter), .clk_en(clk_en));
/*branch output assignation*/
always@(posedge clk)
begin
if(valid_in)
begin
branch_out<=D1;
branch_out<=D2;
branch_out<=D3;
branch_out<=D4;
branch_out<=D5;
branch_out<=D6;
branch_out<=D7;
branch_out<=D8;
branch_out<=D9;
branch_out<=D10;
branch_out<=D11;
branch_out<=D12;
branch_out<=D13;
branch_out<=D14;
branch_out<=D15;
branch_out<=D16;
branch_out<=D17;
branch_out<=D18;
branch_out<=D19;
branch_out<=D20;
branch_out<=D21;
branch_out<=D22;
branch_out<=D23;
branch_out<=D24;
branch_out<=D25;
branch_out<=D26;
branch_out<=D27;
branch_out<=D28;
branch_out<=D29;
branch_out<=D30;
branch_out<=D31;
branch_out<=D32;
end
else for(i=1;i<33;i=i+1)branch_out<=branch_out;
end
/*shift registers*/
always@(posedge clk)
begin
if(valid_in)
begin
case(clk_en)
32'd1:begin D1<=branch_in;end
32'd2:begin D2<=branch_in;D2<=D2;end
32'd4:begin D3<=branch_in;D3<=D3;D3<=D3;end
32'd8:begin D4<=branch_in;for(i=1;i<4;i=i+1)D4<=D4;end //D1<=D0,D2<=D1,D3<=D2
32'd16:begin D5<=branch_in;for(i=1;i<5;i=i+1)D5<=D5;end
32'd32:begin D6<=branch_in;for(i=1;i<6;i=i+1)D6<=D6;end
32'd64:begin D7<=branch_in;for(i=1;i<7;i=i+1)D7<=D7;end
32'd128:begin D8<=branch_in;for(i=1;i<8;i=i+1)D8<=D8;end
32'd256:begin D9<=branch_in;for(i=1;i<9;i=i+1)D9<=D9;end
32'd512:begin D10<=branch_in;for(i=1;i<10;i=i+1)D10<=D10;end
32'd1024:begin D11<=branch_in;for(i=1;i<11;i=i+1)D11<=D11;end
32'd2048:begin D12<=branch_in;for(i=1;i<12;i=i+1)D12<=D12;end
32'd4096:begin D13<=branch_in;for(i=1;i<13;i=i+1)D13<=D13;end
32'd8192:begin D14<=branch_in;for(i=1;i<14;i=i+1)D14<=D14;end
32'd16384:begin D15<=branch_in;for(i=1;i<15;i=i+1)D15<=D15;end
32'd32768:begin D16<=branch_in;for(i=1;i<16;i=i+1)D16<=D16;end
32'd65536:begin D17<=branch_in;for(i=1;i<17;i=i+1)D17<=D17;end
32'd131072:begin D18<=branch_in;for(i=1;i<18;i=i+1)D18<=D18;end
32'd262144:begin D19<=branch_in;for(i=1;i<19;i=i+1)D19<=D19;end
32'd524288:begin D20<=branch_in;for(i=1;i<20;i=i+1)D20<=D20;end
32'd1048576:begin D21<=branch_in;for(i=1;i<21;i=i+1)D21<=D21;end
32'd2097152:begin D22<=branch_in;for(i=1;i<22;i=i+1)D22<=D22;end
32'd4194304:begin D23<=branch_in;for(i=1;i<23;i=i+1)D23<=D23;end
32'd8388608:begin D24<=branch_in;for(i=1;i<24;i=i+1)D24<=D24;end
32'd16777216:begin D25<=branch_in;for(i=1;i<25;i=i+1)D25<=D25;end
32'd33554432:begin D26<=branch_in;for(i=1;i<26;i=i+1)D26<=D26;end
32'd67108864:begin D27<=branch_in;for(i=1;i<27;i=i+1)D27<=D27;end
32'd134217728:begin D28<=branch_in;for(i=1;i<28;i=i+1)D28<=D28;end
32'd268435456:begin D29<=branch_in;for(i=1;i<29;i=i+1)D29<=D29;end
32'd536870912:begin D30<=branch_in;for(i=1;i<30;i=i+1)D30<=D30;end
32'd1073741824:begin D31<=branch_in;for(i=1;i<31;i=i+1)D31<=D31;end
32'd2147483648:begin D32<=branch_in;for(i=1;i<32;i=i+1)D32<=D32;end
default:D1<=branch_in;
endcase
end
end
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continued here:
/*DEINTERLEAVER*/
wire data_in_de;
wire de_valid_in;
assign data_in_de=data_out;
assign de_valid_in=valid_out;
assign de_valid_out=de_valid_in;
reg counter_reg, counter_reg1;
reg clk_en_de;
/*Deinterleaver branches*/
reg DFF1;
reg DFF2 ;
reg DFF3 ;
reg DFF4 ;
reg DFF5 ;
reg DFF6 ;
reg DFF7 ;
reg DFF8 ;
reg DFF9 ;
reg DFF10;
reg DFF11;
reg DFF12;
reg DFF13;
reg DFF14;
reg DFF15;
reg DFF16;
reg DFF17;
reg DFF18;
reg DFF19;
reg DFF20;
reg DFF21;
reg DFF22;
reg DFF23;
reg DFF24;
reg DFF25;
reg DFF26;
reg DFF27;
reg DFF28;
reg DFF29;
reg DFF30;
reg DFF31;
reg DFF32;
wire branch_in_de ;
reg branch_out_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
/*counter delay to compensate data delay*/
always@(posedge clk)
begin
counter_reg1<=counter;
counter_reg<=counter_reg1; //compensate for branch_out and data_out
end
/*instantiate mux and enable control*/
mux_8x32 switch_deint(.counter(counter_reg), .branch_out(branch_out_de), .data_out(deinterleaver_out));
enable_coder en_bus_deint(.counter(counter), .clk_en(clk_en_de));
always@(posedge clk)
begin
if(de_valid_in)
begin
branch_out_de<=DFF1;
branch_out_de<=DFF2;
branch_out_de<=DFF3;
branch_out_de<=DFF4;
branch_out_de<=DFF5;
branch_out_de<=DFF6;
branch_out_de<=DFF7;
branch_out_de<=DFF8;
branch_out_de<=DFF9;
branch_out_de<=DFF10;
branch_out_de<=DFF11;
branch_out_de<=DFF12;
branch_out_de<=DFF13;
branch_out_de<=DFF14;
branch_out_de<=DFF15;
branch_out_de<=DFF16;
branch_out_de<=DFF17;
branch_out_de<=DFF18;
branch_out_de<=DFF19;
branch_out_de<=DFF20;
branch_out_de<=DFF21;
branch_out_de<=DFF22;
branch_out_de<=DFF23;
branch_out_de<=DFF24;
branch_out_de<=DFF25;
branch_out_de<=DFF26;
branch_out_de<=DFF27;
branch_out_de<=DFF28;
branch_out_de<=DFF29;
branch_out_de<=DFF30;
branch_out_de<=DFF31;
branch_out_de<=DFF32;
end
else for(i=1;i<33;i=i+1)branch_out_de<=branch_out_de; //oppure non disturbare
end
/* shift registers*/
always@(posedge clk)
begin
if(de_valid_in)
begin
case(clk_en_de)
32'd2147483648:begin DFF1<=branch_in_de;end
32'd1073741824:begin DFF2<=branch_in_de;DFF2<=DFF2;end
32'd536870912:begin DFF3<=branch_in_de;DFF3<=DFF3;DFF3<=DFF3;end
32'd268435456:begin DFF4<=branch_in_de;for(i=1;i<4;i=i+1)DFF4<=DFF4;end //1<=0,2<=1,3<=2
32'd134217728:begin DFF5<=branch_in_de;for(i=1;i<5;i=i+1)DFF5<=DFF5;end
32'd67108864:begin DFF6<=branch_in_de;for(i=1;i<6;i=i+1)DFF6<=DFF6;end
32'd33554432:begin DFF7<=branch_in_de;for(i=1;i<7;i=i+1)DFF7<=DFF7;end
32'd16777216:begin DFF8<=branch_in_de;for(i=1;i<8;i=i+1)DFF8<=DFF8;end
32'd8388608:begin DFF9<=branch_in_de;for(i=1;i<9;i=i+1)DFF9<=DFF9;end
32'd4194304:begin DFF10<=branch_in_de;for(i=1;i<10;i=i+1)DFF10<=DFF10;end
32'd2097152:begin DFF11<=branch_in_de;for(i=1;i<11;i=i+1)DFF11<=DFF11;end
32'd1048576:begin DFF12<=branch_in_de;for(i=1;i<12;i=i+1)DFF12<=DFF12;end
32'd524288:begin DFF13<=branch_in_de;for(i=1;i<13;i=i+1)DFF13<=DFF13;end
32'd262144:begin DFF14<=branch_in_de;for(i=1;i<14;i=i+1)DFF14<=DFF14;end
32'd131072:begin DFF15<=branch_in_de;for(i=1;i<15;i=i+1)DFF15<=DFF15;end
32'd65536:begin DFF16<=branch_in_de;for(i=1;i<16;i=i+1)DFF16<=DFF16;end
32'd32768:begin DFF17<=branch_in_de;for(i=1;i<17;i=i+1)DFF17<=DFF17;end
32'd16384:begin DFF18<=branch_in_de;for(i=1;i<18;i=i+1)DFF18<=DFF18;end
32'd8192:begin DFF19<=branch_in_de;for(i=1;i<19;i=i+1)DFF19<=DFF19;end
32'd4096:begin DFF20<=branch_in_de;for(i=1;i<20;i=i+1)DFF20<=DFF20;end
32'd2048:begin DFF21<=branch_in_de;for(i=1;i<21;i=i+1)DFF21<=DFF21;end
32'd1024:begin DFF22<=branch_in_de;for(i=1;i<22;i=i+1)DFF22<=DFF22;end
32'd512:begin DFF23<=branch_in_de;for(i=1;i<23;i=i+1)DFF23<=DFF23;end
32'd256:begin DFF24<=branch_in_de;for(i=1;i<24;i=i+1)DFF24<=DFF24;end
32'd128:begin DFF25<=branch_in_de;for(i=1;i<25;i=i+1)DFF25<=DFF25;end
32'd64:begin DFF26<=branch_in_de;for(i=1;i<26;i=i+1)DFF26<=DFF26;end
32'd32:begin DFF27<=branch_in_de;for(i=1;i<27;i=i+1)DFF27<=DFF27;end
32'd16:begin DFF28<=branch_in_de;for(i=1;i<28;i=i+1)DFF28<=DFF28;end
32'd8:begin DFF29<=branch_in_de;for(i=1;i<29;i=i+1)DFF29<=DFF29;end
32'd4:begin DFF30<=branch_in_de;for(i=1;i<30;i=i+1)DFF30<=DFF30;end
32'd2:begin DFF31<=branch_in_de;for(i=1;i<31;i=i+1)DFF31<=DFF31;end
32'd1:begin DFF32<=branch_in_de;for(i=1;i<32;i=i+1)DFF32<=DFF32;end
default: DFF1<=branch_in_de;
endcase
end
end
endmodule
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