transfer VHDL bi-ports to Verilog bi-ports

[Altera_Forum]

Hi! 

I have been working on transfering a VHDL file to a verilog one. Bidirectional port of D didn't work well... This VHDL file can work on CPLD while the verilog file cann't...  PS:Formality reports that D didn't math... Result of my checking in Formality shows that there is no difference between them. tks! U can download them from attachments.

[Altera_Forum]

Why do you think that the problem is related to bidirectional pin implementation? The coding of this design detail seems equivalent at first sight. As an obvious difference, the state machine is encoded with default one-hot style in Verilog, while it's binary (user) encoded in VHDL. According to the file comments, the binary encoding is required. 

 Please consider that Altera synthesis attributes can't be translated by X-HDL.   Generally, you would set up a test bench and find out in simulation what goes wrong in Verilog conversion.

[Altera_Forum]

hi, FvM 

thks for your reply. The state machine in Verilog is encoded in 4-bit binary, too. For example, '0, 1, 2, ..., 15', not one-hot of '1, 2, 4, ...,65535 '(in dec).

[Altera_Forum]

--- Quote Start ---  The state machine in Verilog is encoded in 4-bit binary, too.  --- Quote End ---   Did you look at the gate level net list?