Constraint the path between CPU and FPGA

[Altera_Forum]

hi, all 

I want to constrain the path between CPU and FPGA. Timing diagram bellow is cutting from the datasheet of CPU current contraints： 1. address latch enable input port, set_input delay for both rise and fall edge set_input_delay -rise -max -clock [get_clocks {CLK}] t11max [get_ports {ALE}] set_input_delay -rise -min -clock [get_clocks {CLK}] t11min [get_ports {ALE}] set_input_delay -add_delay -fall -max -clock [get_clocks {CLK}] t21max [get_ports {ALE}]  set_input_delay -add_delay -fall -min -clock [get_clocks {CLK}] t21min [get_ports {ALE}]  2. ship select input port set_input_delay -rise -max -clock [get_clocks {CLK}] t24max [get_ports {CPU_CS1 CPU_CS2}] set_input_delay -rise -min -clock [get_clocks {CLK}] t24min [get_ports {CPU_CS1 CPU_CS2}] set_input_delay -add_delay -fall -max -clock [get_clocks {CLK}] t14max [get_ports {CPU_CS1 CPU_CS2}]  set_input_delay -add_delay -fall -min -clock [get_clocks {CLK}] t14min [get_ports {CPU_CS1 CPU_CS2}]   3. read and write input port set_input_delay -rise -max -clock [get_clocks {CLK}] t20x [get_ports {CPU_WRH CPU_WRL}] set_input_delay -rise -min -clock [get_clocks {CLK}] t20n [get_ports {CPU_WRH CPU_WRL}] set_input_delay -add_delay -fall -max -clock [get_clocks {CLK}] t10max [get_ports {CPU_WRH CPU_WRL}]  set_input_delay -add_delay -fall -min -clock [get_clocks {CLK}] t10min [get_ports {CPU_WRH CPU_WRL}]  4. FPGA-TO-CPU data output port set_output_delay -clock {get_clocks {CLK}} -max t30 [get_ports {CPU_D}] -add_delay set_output_delay -clock {get_clocks {CLK}} -min t31 [get_ports {CPU_D}] -add_delay  Are the constraints above correct? And I'm little confused how to contrain CPU-TO_FPGA input port? Thx