Quartus II : Problems with VHDL records?

[Altera_Forum]

I have a problem with the synthesis of my design: 

 A component has an AXI slave interface. In the architecture of this component the AXI signals are being combined into a record an then assigned to deeper hierarchy levels.  When synthesizing this component I get error 10031 which says that I'm driving a signal from multiple sources.  I checked a gazillion times and I'm absolutely sure that this is not the case - not in this file and not in any other file being used in the design. A strange point is that Quartus says that all 4 bits of a 4 bit input signal (ARLEN) are being assigned to the MSB of the record signal AXI_RECORD.ARADDR  To me it looks like Quartus might have some issues with records. Is this true or are there other reasons for this error (as I said previously I can rule out VHDL errors causing what 10031 says).

[Altera_Forum]

Are you sure about the multiple drivers? I think its a multiple driver problem if you drive different record elements from different processes, or different bits of a record element.  

 Does the design simulate ok? do you get any 'XXX' values anywhere?  Can you show the code with the declaration of the record and where it is used/assigned?

[Altera_Forum]

Unfortunately I cannot show the code. But I could solve the problem. Apparently it was the AXI record. After I removed the record and assigned all signals individually Quartus did not report any more errors