bandwidth for Cyclone IV(-8 grade) and 32-bit DDR2 SDRAM

[Altera_Forum]

I want to use Cyclone IV(-8 grade) and 32-bit DDR2 SDRAM to store 

some high bandwidth AD conversion results. But I am not sure if this configuration is feasible or not. Could you please help to answer: - 256-pin or 324-pin Cyclone IV is used, with up to 179 or 193 user I/O pins - 32-bit DDR2 SDRAM with clock at 400MHz , two 16-bit chips are used, total size is 512MB. They need about 50 I/O pins. - 8 channels 8-bit ADC are connected to Cyclone4, with clock at 100MHz, data is produced at 8*100 = 800MBytes/s. They need about 80 I/O pins.   I suppose bandwidth for DDR2 is about 400*2*4*0.5 = 1600M Bytes/s. Here I assume read/write efficiency is 0.5. So, I think 512MB DDR2 SDRAM should be able to store about 0.5 second continous ADC conversion results. Besides, 256-pin(F256 package) Cyclone IV EP4CE6/10 seems enough to support this task. Am I right ?  thanks for your opinion!

[Altera_Forum]

In general is sounds ok. Be careful on bank usages. 

 Unless the DDR2 and ADC use the same IO voltage, they will require different banks, so you'll have some wasted IO's due to this limitation.  If you are using LVDS there are rules associated with these IO's around and adjacent single ended IO's as well.  My recommendation is you complete a top level design back box that connects all the IO's that will be used, and has minimal logic to insure the IO's are not optimized out.  DDR2 timing can be difficult, so the -8 speed grade may give you difficulties here. (I haven't played with that side much).. (Much easier with Cyclone V with the hard memory controllers)  Your size requirements really depends on what else you need to do in the device. If you can do the entire design and have plenty of resources left over you are good, but designs tend to grow over time, so I tend to pick the middle family size for a targeted package is I think I'm IO limited, but make sure the board is capable of migrating up and down for the device family.  This is not as easy as it appears, Many of the "Migration" paths have IO that are either VCC/GND pins or NC pins when you migrate up and down. So you want to closely look at all package family members to make sure you have it right, and have the migration devices selected in your pinout as well in quartus.  If this is just a one-off or small number of boards, it may be much easier to get what you need by building a daughter card using the HSMC connectors for your ADC's and using an off the shelf dev board like the SOC kit that already has the ram and interfaces you need.  Pete

[Altera_Forum]

anakha, thanks a lot for your comment! 

You give me many good hints: IO voltage, pin assignment, ...  I would like to use parallel interface for ADC, but now it seems better to use LVDS to save pins. besides -8 grade may be slow, I need to consider -6 grade for Cyclone IV. I check and find Cyclone IV can only support up to 200MHz DDR2 clock, so perhaps I need Cyclone V which supports up to 400MHz DDR2 clock [@ Altera's External Memory Interface Solutions Center].

[Altera_Forum]

I think you may be much happier with Cyclone V. DDR2 timing can be tricky. If size is not the limit, the U484 package has the full migration range for a 19x19 package. 

 The only problem with Cyclone V is you need the magic decoder ring to figure out the correct part to buy. You want to make sure you get the variation with the hard memory controllers.  The decoder ring is in this document. http://www.altera.com/literature/hb/cyclone-v/cv_51001.pdf Page 5 has the E variation decoder.  Based on what you've told me, I would assume you would want the 5CEFA2U19C8N or possibly 5CEFA2U15C8N parts  Looking at Arrow, the U15 part may me rare still. I'm only seeing F23 parts in stock right now. http://components.arrow.com/part/search/5cefa2  These are a significant premium over the Cyclone V family members you were looking at, but they are larger devices, 25k vs 6k or 10K LE's. But it should be much easier on timing.  Pete