AXI read channel - signal rlast "missing"

[Altera_Forum]

Hi, 

 I try to get familiar with the AXI protocol. Therefore, I extended an example Design that comes along my EBV SoCrates Board (Lab1_solution). I use Quartus II Subscription Edition V13.1 under Debian Linux.  I created a custom component in QSYS that implements the AXI3 Interface. I added it to the existing system at the LWHPS2FPGA Interface at an Address 0x20000 which for the Linux that runs in the HPS is at address 0xff220000. I have (from the example design) also a LED test component (Avalon MM Slave) that is accessible under 0xff200000 from the Linux on the HPS. Under Linux, in order to test the data transfer to the custom conponents, I use the tool devmem2. With that tool, I can switch on/off LEDs under the aforementioned LED component address.  Now, my AXI component just implements the Read address- and data-channels in order to read a counter value from that component with devmem2 from Linux. I added signal tap to my custom component in oder to observe the data transaction. In my understanding of the AXI data channel specification it is mandatory to switch the "rlast" signal from the slave once the last element of the data transfer is put on the bus. I implemented that signal in my custom component, but I'm not able to signal tap it because it is not in the post fitting netlist of my design (however, the wlast signal is there although I do not connect it in my test component.  The result of my devmem2 test from the Linux side is, that the call looks like a blocking call, that is never finished. In my opinion that is because the rlast signal is not applied and therefore the AXI transaction is not complete.  If you look at the attached signal tap screenshot then you see, that (after issuing the request from Linux) the correct address is called and the counter value is put onto the rdata bus. The only thing that is missing is the rlast signal that I do set in my vhdl component but I do not have a connection available in the QSYS generated component "SOC_System_hps_0_fpga_interfaces:fpga_interfaces...."  Additionally, I attach my custom component vhdl and tcl files in order for you to examine if I did something wrong there or if this maybe a bug in QSYS interconnect builder/Quartus Tool, that just not offers the rlast signal after synthesis/fitting.  I'm interested in your opinions on that.  Regards, Maik

[Altera_Forum]

If you want to prevent nets from being optimized away you can try this (I copied this from the VHDL templates in Quartus II): 

 -- Prevents Quartus II from minimizing or removing a particular -- signal net during combinational logic optimization. Apply -- the attribute to a net or variable declaration. attribute keep : boolean;  attribute keep of <object> : <object_class> is true;   Unfortunately I don't remember VHDL well enough to know how that code is supposed to behave. The lack of a defined reset condition is throwing me off.

[Altera_Forum]

Hi BadOmen, 

 Thanks for your answer! However, I doubt, that my problem is to be solved by advising Quartus to prevent some of my logic being optimized away.  I mean, the rlast signal is defined in the ARM AXI documentation and therefore, if QSys is AXI compatible, the according master in my system (the LWHPS2FPGA bridge) shoulkd implement that signal, too. QSys should be able to connect my AXI compatible slave to the AXI compatible master correctly and therefore should take care that specification signals should not be "optimized" away. So I think, that there could be three reasons for my problem:  First, I misunderstand the AXI protocol and therefore did not handle the master read in my component correctly. This would include that the rlast signal isn't required at all and I'm focusing on the wrong thing here. This could be because I do not find ANY rlast signal in my whole system. As I said, the LED Avalon memory slave component works fine via the LWHPS2FPGA bridge. I know that the QSys interconnect connects the Avalon slave to the AXI master in the bridge and maps all required signals properly in order to obay their specifications. Now, if I do not find any rlast signal in my design, then why is the interconnection between avalon and AXI working in the LED slave? In my opinion there, too, must be a rlast signal at a certain conversion level.  Second, I do not handle the signals arlen, arburst, arsize correctly in my component and therefore, the read on my component fails. I know, that I do not handle those signals at all in my component. That is because I do not think, that (with the given data on that signals that can be seen in the Signal Tap shot) I do not have to handle anything because it is a single 32bit read by the master on my component so that I just put one 32 bit value on the read data bus and set all handshake lines correctly. But maybe sombody does find that this is not eneough. I would be happy about any advise.  Third, there is an error in the QSys interconnect generator that it just does not care about the rlast signal. I do not believe that this is the case but it should be on my list, I think.  I would be happy if I could find any working example of an AXI component in VHDL that I can connect to the LWHPS2FPGA or HPS2FPGA Masters of the Cyclone V. But until now, I was not able to find one. I just do find avalon custom component examples where the QSys interconnect takes care of protocol conversion.  I really want to use AXI in my upcoming project because I would like to use similtanious writes and reads without any data buffering or additional stuff between the AXI master and slave.  Regards, Maik