Program Counter using VHDL for Altera DE2 Board.

[Altera_Forum]

Hi guys noob here, first post. I need to design a program counter to satisfy the following schematic.  

  https://www.alteraforum.com/forum/attachment.php?attachmentid=8350    and here is my code so far. Now I'm pretty sure this is wrong. But I don't even know how to test this yet using QuartusII, hoping my TA will explain it this Monday. Would someone with more experience take a look and help me figure this out, in particular I am sure I implemented the inc (increment) condition wrong, that is, if inc is high then I should start the count from the output.     LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY pc IS PORT( clr : IN STD_LOGIC; clk : IN STD_LOGIC; ld : IN STD_LOGIC; inc : IN STD_LOGIC; d : IN STD_LOGIC_VECTOR(31 DOWNTO 0); q : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END pc; ARCHITECTURE description OF pc IS -- you fill in what goes here!!! SIGNAL Count:STD_LOGIC_VECTOR (31 DOWNTO 0) ; BEGIN PROCESS (clk,clr,ld,inc) BEGIN IF clr='0' THEN Count<="00000000000000000000000000000000"; ELSIF inc='1' THEN Count<=q; ELSIF (clk'EVENT AND clk = '1') THEN IF ld='1' THEN Count<=Count+4; ELSE Count<=Count; END IF; END IF; END PROCESS; q<=Count; END description;    any help would be greatly appreciated, thanks in advanced.

[Altera_Forum]

Just one minor adjustment: 

Inc shouldnt be asynchronous. Also you shouldnt have a situation where an async event holds the value of q. This will cause a latch.

[Altera_Forum]

Hopefully, your instructor will show you have to create a VHDL testbench and use modelsim.

[Altera_Forum]

--- Quote Start ---  Just one minor adjustment: Inc shouldnt be asynchronous. Also you shouldnt have a situation where an async event holds the value of q. This will cause a latch.  --- Quote End ---    ok thanks for that Tricky, my TA (teaching assistant) showed me how to run the simulations so I will try it this week. I'm surprised you say this code is ok. But isn't a latch what I want? that is, I want to hold the value of q in case I want to start at that number??  Again sorry if I'm not making sense, I'm just a beginner, in vhdl that is. I do have some knowledge on logic gates and making circuits from them.   Thanks Again, Ill be back here for my next lab no doubt.

[Altera_Forum]

THere are no latches in an FPGA, only LUTs and registers. A synchronous register can hold the value for you. Latches are prone to glitching and cannot be analysed for timing, so are heavily discouraged in an FPGA (and you will get warnings when they are created in the synthesisor.

[Altera_Forum]

--- Quote Start ---  THere are no latches in an FPGA, only LUTs and registers. A synchronous register can hold the value for you. Latches are prone to glitching and cannot be analysed for timing, so are heavily discouraged in an FPGA (and you will get warnings when they are created in the synthesisor.  --- Quote End ---    ok thanks Tricky, so you're saying that I should put the if inc=1 condition under the event clock condition, correct?

[Altera_Forum]

Yes. 

All the ifs/elsifs/case statements inside a clocked part of a process will map to logic gates, with the final assignment being the actual register.

[Altera_Forum]

--- Quote Start ---  Yes. All the ifs/elsifs/case statements inside a clocked part of a process will map to logic gates, with the final assignment being the actual register.  --- Quote End ---    Got it, will do. Thanks again.