synthesizable VHDL subset

[Altera_Forum]

Call me an idealistic noob, but it does not seems that Altera provides any description of the VHDL subset which can be synthesizable by its tools, and this bothers me a lot. 

 Still pass the VHDL standard does not address this issue, but as a tool provider why does Altera not seem to bother to define this?  Does anyone shares my feelings?  And where could I found this so precious information???

[Altera_Forum]

Is this what you're looking for? 

http://quartushelp.altera.com/13.1/mergedprojects/hdl/vhdl/vhdl_intro.htm http://quartushelp.altera.com/13.1/mergedprojects/hdl/vhdl/vhdl_list_support.htm

[Altera_Forum]

Not really, ted... 

 Those documents only describe which parts of the IEEE Standard VHDL Language Reference Manuals are supported by the Quartus tools. But these language reference manuals define only simulation semantics of the language.  I would like a synthesis semantics for the Altera tools. I am looking for a kind of "IEEE 1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis" for VHDL 2008 as implemented by Altera. A little bit like http://gcc.gnu.org/onlinedocs/gnat_rm/implementation-defined-characteristics.html#implementation-defined-characteristics, defining how a given compiler implements the Ada language definition...

[Altera_Forum]

There is no synthesisable "subset" of any HDL. HDL stands for "hardware description language". So you are just discribing a circuit behaviour. Then the tools try and understand your code to translate it into hardware. The thing is, the tools generally get better with each version as to what code they can translate into real hardware. 

 Altera does provide a chapter in the Quartus handbook, entitled "Recommended HDL coding styles" (http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf) which descibe how you should write your behavioural code to get the synthesisor to translate it into the basic elements of the chip. This chapter has been included in the handbook for as long as I have been coding VHDL (8+ years).

[Altera_Forum]

Well, this  

--- Quote Start ---  what code they can translate into real hardware.  --- Quote End ---   is exactly this synthesisable subset. Just a pity that it is not explicitly defined, but must be discovered by trials and errors.  The only relevant document I found was http://www.altium.com/files/learningguides/tr0115%2520vhdl%2520synthesis%2520reference.pdf , but it is old, and from Alt(era)ium  The more I use and discover text-based hardware generation, the more I am amazed, both positively and negatively, by the way it is used ;-)

[Altera_Forum]

I regard IEEE Std 1076.6 as the description of a "synthesizable VHDL subset". Although it's not strictly supported by Altera, the description applies more or less to all VHDL synthesis tools.

[Altera_Forum]

--- Quote Start ---  Just a pity that it is not explicitly defined, but must be discovered by trials and errors.   --- Quote End ---    It is difficult to define exactly what is and what isnt supported. VHDL is a behavioral language. The synthesisor tries to translate the bahaviour into gates and registers (and memories, tri-states, etc). Plus the fact different chip families have different architectures, so the same code will map to different things on different chips.  The best you can get is the chapter I mentioned - it is the best place on how to learn how to write good, re-usable VHDL. Plus the IEEE std 1076.6 outlines the basic structure for synthesisable VHDL code, which is taught in many text books and tutorials (even by altera itself).