Cyclone V SerialLite-II

[Altera_Forum]

Hello all, 

 I am trying to impement SerialLite-II on a Cyclone V. I have my design to the point where I can simulate it successfully, but synthesis fails with the following error:  warning: outclk port on the pll is not properly connected on instance main_pll:u_main_pll|main_pll_0002:main_pll_inst|altera_pll:altera_pll_i|general[0].gpll. the output clock port on the pll must be connected.  info: must be connected error: hssi pma tx buffer node 'impl_top:dut|sl2_top:u_sl2_top|xcvr_phy:u_xcvr_phy|altera_xcvr_custom:xcvr_phy_inst|av_xcvr_custom_nr:a5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'dataout' port. it must be connected to one of the valid ports listed below.  info: can be connected to i port of arriav_io_obuf wysiwyg error: hssi pma rx buffer node 'impl_top:dut|sl2_top:u_sl2_top|xcvr_phy:u_xcvr_phy|altera_xcvr_custom:xcvr_phy_inst|av_xcvr_custom_nr:a5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf' is not properly connected on the 'datain' port. it must be connected to one of the valid ports listed below.  info: can be connected to o port of arriav_io_ibuf wysiwyg  info: can be disconnected  Altera changed the way the core is created with the V-series and separated the PHY from the core in the megawizard. This may add more flexibility in the design, but certainly adds more complexity (and room for error) in the connections between the blocks. I particularly enjoyed the reference in the error to ArriaV...  Has anyone out there been successful with their SerialLite implementation on Cyclone V? Any insights?  Thanks in advance!

[Altera_Forum]

Found out that the top-level ports were being disabled, causing the synthesizer to rip out the lower level instantiations. Still need to verify in hardware, but I look to be through the weeds. 

 The FAE provided a sample 4-ch SerialLite design targeting the Cyclone-V if anyone is interested. It is not posted on the website.

[Altera_Forum]

--- Quote Start ---  Found out that the top-level ports were being disabled, causing the synthesizer to rip out the lower level instantiations. Still need to verify in hardware, but I look to be through the weeds.  The FAE provided a sample 4-ch SerialLite design targeting the Cyclone-V if anyone is interested. It is not posted on the website.  --- Quote End ---     Hi Jcosper,  Are you able to share me the Cyclone V Seriallite II example?  Rgds, Felix

[Altera_Forum]

Hi Jcosper, 

 Can You share the Cyclone V Seriallite II example to me as i have hard time get it to work ?  Rgds, Jingrui

[Altera_Forum]

Sorry for the delay... 

 I attached the QAR example for SerialLite-II that I received. Good luck! I was able to get 2.5Gbps links verified in hardware on a TerASIC SoC Kit.  Jay

[Altera_Forum]

BTW, proper configuration of the transceivers is key, and generally, you need to avoid using the middle of transceiver triplets if you want full-duplex. But this depends heavily on your particular design. It took a while of digging through documentation for find valid transceiver configurations.

[Altera_Forum]

--- Quote Start ---  BTW, proper configuration of the transceivers is key, and generally, you need to avoid using the middle of transceiver triplets if you want full-duplex. But this depends heavily on your particular design. It took a while of digging through documentation for find valid transceiver configurations.  --- Quote End ---   2 Questions: 1. Why to avoid using the middle of transceiver triplets if I want full-duplex? 2. The controller in your design is necessary? what is part if I don't want to reconfig anything?

[Altera_Forum]

From the Transceiver Clocking document (http://www.altera.com/literature/hb/cyclone-v/cv_53002.pdf): 

"When you configure the channel PLL as a CMU PLL to drive the local clock divider, or the central clock divider of its own channel, you cannot use the channel PLL as a CDR. Without a CDR, you can use the channel only as a transmitter channel."  One of the central transceivers has to be used for the local clock divider for full-duplex use. You get to pick which, but the one that you pick can only be TX afterwards (so no full-duplex).  The design is not mine, but a reference design provided by Altera SR. The reconfiguration controller (I assume that is what you are asking about) is required even if you don't want to use reconfiguration. As long as the reference clock is the same for all channels/protocols, one reconfiguration controller may be shared across all transceiver channels. Just change the reconfiguration controller IP in the MegaWizard to match the reconfiguration inputs to your module. Remember that you need one reconfiguration interface per discrete link, and one per channel in the link. For example, with a x4 PCIe link, I need 5 reconfiguration interfaces (1 for link, 4 for each lane). With four x1 SerialLite-II links, I needed eight reconfiguration interfaces. And so on...  Hope this helps.

[Altera_Forum]

--- Quote Start ---  From the Transceiver Clocking document (http://www.altera.com/literature/hb/cyclone-v/cv_53002.pdf): "When you configure the channel PLL as a CMU PLL to drive the local clock divider, or the central clock divider of its own channel, you cannot use the channel PLL as a CDR. Without a CDR, you can use the channel only as a transmitter channel."  One of the central transceivers has to be used for the local clock divider for full-duplex use. You get to pick which, but the one that you pick can only be TX afterwards (so no full-duplex).  The design is not mine, but a reference design provided by Altera SR. The reconfiguration controller (I assume that is what you are asking about) is required even if you don't want to use reconfiguration. As long as the reference clock is the same for all channels/protocols, one reconfiguration controller may be shared across all transceiver channels. Just change the reconfiguration controller IP in the MegaWizard to match the reconfiguration inputs to your module. Remember that you need one reconfiguration interface per discrete link, and one per channel in the link. For example, with a x4 PCIe link, I need 5 reconfiguration interfaces (1 for link, 4 for each lane). With four x1 SerialLite-II links, I needed eight reconfiguration interfaces. And so on...  Hope this helps.  --- Quote End ---    Can I get your email address for a few more questions if you don't mind? Thanks!

[Altera_Forum]

--- Quote Start ---  From the Transceiver Clocking document (http://www.altera.com/literature/hb/cyclone-v/cv_53002.pdf): "When you configure the channel PLL as a CMU PLL to drive the local clock divider, or the central clock divider of its own channel, you cannot use the channel PLL as a CDR. Without a CDR, you can use the channel only as a transmitter channel."  One of the central transceivers has to be used for the local clock divider for full-duplex use. You get to pick which, but the one that you pick can only be TX afterwards (so no full-duplex).  The design is not mine, but a reference design provided by Altera SR. The reconfiguration controller (I assume that is what you are asking about) is required even if you don't want to use reconfiguration. As long as the reference clock is the same for all channels/protocols, one reconfiguration controller may be shared across all transceiver channels. Just change the reconfiguration controller IP in the MegaWizard to match the reconfiguration inputs to your module. Remember that you need one reconfiguration interface per discrete link, and one per channel in the link. For example, with a x4 PCIe link, I need 5 reconfiguration interfaces (1 for link, 4 for each lane). With four x1 SerialLite-II links, I needed eight reconfiguration interfaces. And so on...  Hope this helps.  --- Quote End ---    I can't see the pinout in this project, can you post the pin locations you chose? There is 2 banks - 0 and 1 - each have 3 transceivers(rx and tx) and 1 ref_clk.

[Altera_Forum]

Hello Jay, 

 I used the QAR example that you have attached foe seriallite II for Cyclone V GX. I wanted to change the parameters for 5CGXFC3B7F23C8N, but parameters for seriallite II IP cannot be reached. there is some error to edit parameters or upgrade it. I could not find *.bsf file for seriallite II in the QAR file. I think that this is the problem. Would you please help me in this regard?  Regards, AHz    --- Quote Start ---  Sorry for the delay...  I attached the QAR example for SerialLite-II that I received. Good luck! I was able to get 2.5Gbps links verified in hardware on a TerASIC SoC Kit.  Jay  --- Quote End ---  

[Altera_Forum]

I can't locate the qsys file in the archive. Can you help? thanks

[Altera_Forum]

Jay,  

I can't find the qsys file in the archived file. Can you help?   Thanks