Hi,
I have an issue with HPS hard DDR3 calibration on the Cyclone V SoC device. I have two boards (the same PCB), one with a single DDR3 device fitted (1Gb x 16) and the other with three devices fitted (1Gb x 40). Both show the same symptom. The preloader fails at during the sdram_calibration_full routine and I am get the following output from the UART.
SEQ.C: CALIBRATION FAILED
SEQ.C: Calibration Summary
SEQ.C: Calibration Failed
SEQ.C: Error Stage : 1
SEQ.C: Error Substage : 1
SEQ.C: Error Group : 0
I am under the impression that this is the very first stage of calibration and that this is a guaranteed read fail?
I am using an LP2998 DDR regulator to provide the termination and reference voltages. I've noticed that the VREF is sitting at around 850mV when I turn the board on and then this reduces to 805mV when I run the preloader. The Vtt rail is sitting at 745mV.
I have searched and found a known problem with the VREF pin on these HPS devices -
http://www.altera.co.uk/support/kdb/solutions/rd09202013_752.html but I am using 13.1 with update 1 applied. Is this still a known issue?
I'm not entirely sure that this is my problem, but I think it must be something fairly fundamental for the calibration to fail at first stage.
Thanks.
