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Input problem for PLL block

Altera_Forum
Honored Contributor II
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Hi Everyone, 

 

I am thinking using PLL for clock derivation,but I have a problem for PLL inputs.There are 11 inputs for PLL and I wanna use multiplexer (created in FPGA) before PLL to select one of them as a input for PLL.but As I see PLL don't accept multiplexer output as input. I think I have to route Muxtiplexer output to FPGA output and then , I have to take it as a input from another FPGA pin.So,I can use this signal for PLL input. but I don't want to waste FPGA pins. 

 

Do you any idea How can I use multiplexer outputs for PLL inputs ? If you share your ideas ,I really appreciate this. 

Thanks in advance
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Altera_Forum
Honored Contributor II
276 Views

 

--- Quote Start ---  

Hi Everyone, 

 

I am thinking using PLL for clock derivation,but I have a problem for PLL inputs.There are 11 inputs for PLL and I wanna use multiplexer (created in FPGA) before PLL to select one of them as a input for PLL.but As I see PLL don't accept multiplexer output as input. I think I have to route Muxtiplexer output to FPGA output and then , I have to take it as a input from another FPGA pin.So,I can use this signal for PLL input. but I don't want to waste FPGA pins. 

 

Do you any idea How can I use multiplexer outputs for PLL inputs ? If you share your ideas ,I really appreciate this. 

Thanks in advance 

--- Quote End ---  

 

 

The PLL ref input must be clean signal relative to PLL requirements. You can use one ref clock into a PLL with multiple outputs then insert a clock mux afterwards on various PLL outputs
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Altera_Forum
Honored Contributor II
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You will not be able to implement a multiplexer on the input to the PLL without an external loop. However, this introduces noise - something the PLL doesn't like. 

 

In addition, in specifying the PLL parameters you are specifying the input frequency. If you then chose one of a number of different frequency clocks then you end up working outside the input frequency range of the PLL you've designed. This may well work but I wouldn't recommend this. 

 

If you're intending to use multiple clocks of the same frequency but different phases - that's OK. However, multiplexing one of these internally and routing it back externally is very likely to introduce different delays to each clock, which will in turn ruin the phase shifted clocks you had to start with. 

 

As Kaz suggested, generate multiple PLL outputs and operate from one of them via a mux. 

 

Regards, 

Alex
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Altera_Forum
Honored Contributor II
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Thanks Kaz and Alex , 

 

Yeah , they have same frequency but different phases , I didn't think about delay and now I guess It will be problem because the frequency is 10 MHz.It is seen that there is no clock selection unit (megafunctions , IP Core something like this ) to select and route for PLL.Then, I should find another solution .  

Thanks again, 

 

Best Regards, 

İbrahim
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