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Neuron implementation in VHDL (code attached)

Altera_Forum
Honored Contributor II
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Hi all.I am just learning VHDL and as an exercise, I am trying to model a neuron in VHDL (attached the code). The neuron has three inputs, three weights and one threshold value (as entity inputs).The neuron is selected through the enableIN and if it is set as '1' ,the neuron reads the inputs, weights and threshold.After that, I created three process for calculate a product between inputs and weights, a sum of these products and at the end a sigmoid function of that summation.What I would like to know is if I wrote these data-flow and behavioral models inside the entity as It is expected to work.The objective is the output having the result of the function when enableOUT is set '1'.I appreciate any help, thanks.

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Altera_Forum
Honored Contributor II
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There are several problems with this code: 

 

1. The first part of the code isnt in a process. 

2. the calculation parts are not synchronous (this mens they will work very slowly) 

3. There is no output 

 

This code is clearly incomplete. I suggest you complete it, write a testbench and see if it functions correctly.
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Altera_Forum
Honored Contributor II
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I also suggest removing the std_logidc_arith and std_logic_unsigned packges as you're using the fixed pckage. They are non stndard libraries and I forsee all sorts of problems if you continue with them.

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Altera_Forum
Honored Contributor II
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Thank you very much for your corrections. 

 

Could you suggest me how to guarantee that all process are synchronous? 

 

maybe if I test the rise edge in the input CLK for all process? 

 

Thanks,
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Altera_Forum
Honored Contributor II
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Yes. Using the rising edge of clk is the way synchronous design works

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Altera_Forum
Honored Contributor II
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Hello dear,  

 

I took an example from a book (commented in code) and I made some modifications. 

 

 

The code (attached) model a layer with three neurons in which I am intending to make a component and create a neural network from it later. 

 

 

The code was compiled and is syntactically correct. 

 

 

My doubt is about this piece of code, where there is a shift register operation: 

-- shift register inference. 

if(clk'event and clk='1') then 

weight:= w & weight(1 to n*m-1); 

end if; 

 

 

That logical AND operation between the input vector of bits 'w' (assuming that it is considered to be a vector of bits) and the 'weight' array of type 'w', is to be considered occurring between 'w' and all elements of 'weight' inside the 'if' statement? 

 

 

Or just between the first elemente of 'weight'? 

 

 

Sorry if this doubt could seem simple, I am comming from languages like C/java. 

 

 

I am looking for a intuitive explanation about this shifting register operation. It seems to differ from the logical n-bits shifting which I know. 

 

thanks,
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Altera_Forum
Honored Contributor II
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Lots of problems with the code. You can clearly see you've come from a C/Java background 

 

I suggest starting again, as the style of the code is not suitable for FPGA implementation. HDL stands for hardware description language. Your code doesnt look like its going to produce any useful hardware. I suggest starting again - start with a peice of paper and draw your circuit. How do you expect to write the code if you dont know roughly what the circuit should be? Only then should you write the HDL. 

 

Forget all your C/Java skills for now. VHDL is completly different. 

 

And Note: & is concatenate in VHDL, not a logical operator.
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Altera_Forum
Honored Contributor II
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Since you cited to start from a piece of paper, I could'nt spend my chance to show my drawing abilities (attached)... so 

 

The code I sent the last post is just my try to make a component for a global entity referred as the ANN entity in the drawing. 

 

So the entity nn_layer has no meaning for itself, but if it will be a component for a global entity, does it make sense based on my drawing?
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Altera_Forum
Honored Contributor II
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I have no idea what nn_layer does. Your drawing is very basic, and bares no relation to the RNA code you posted

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Altera_Forum
Honored Contributor II
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Each nn_layer represents a set of 3 neurons in which we have the same x1,x2 and x3 as inputs for each of neuron. 

 

As neurons, we can think of a sigmoid function of the outputs y1,y2 and y3, which I will implemente after, because it does not affect the architecture of the problem. The sigmoid will be implemented (aproximated) as lookup table. 

 

Before that inputs x1,x2, and x3 are presented to the neurons (sigmoids) they are multiplied by their respectives and uniques 'w's loaded from the ROM. 

 

These yn outputs are passed from one nn_layer entity to the nexts nn_entity. I need 3 nn_layer entities in total. 

 

These 3 nn_layer entities will be modeled as one unique entity (ANN) tha will control the ROM access and provide clock. 

 

The mux are irrelevant and will convert serial to paralell information from the external. 

 

I attached another figure from the book, it is very intuitive and use the variables names that I am using in the code. I is a nn_layer representation. 

 

Thank you very much for your patience and help.
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Altera_Forum
Honored Contributor II
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I suggest you stop using variables. It will not produce the code you expect. You should be using signals to transport data around.

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Altera_Forum
Honored Contributor II
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thanks, I will use signal, but just for the outputs, as I want transport data between components. 

The rest of variables are used just in local processing. 

 

To ending my doubts, the code: 

 

-- shift register inference. 

if(clk'event and clk='1') then 

weight:= w & weight(1 to n*m-1); 

end if; 

 

Mean to read 'w's from ROM in the order (clock) that it comes from, inside the variable 'weight'.
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Altera_Forum
Honored Contributor II
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please stop using variables. In your code they do not create the registers you think they are. There is no such thing as "local processing" your code gets converted into logic gates and registers - THIS is the circuit you need to be thinking about.

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Altera_Forum
Honored Contributor II
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You are also not using the proper templates for synthesisable HDL code.

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Altera_Forum
Honored Contributor II
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OK, I will use signals, thanks. 

 

What do you mean with " proper templates"? 

 

Please, can you indicate me some book?  

 

I am reading these ones: 

 

Circuit Design with VHDL, free range vhdl and Fundamentals of Digital Logic.  

 

 

thanks,
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Altera_Forum
Honored Contributor II
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That should be ok. But I also suggest any decent VHDL tutorial. 

 

Also have a look at the altera HDL coding guidlines 

http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf
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Altera_Forum
Honored Contributor II
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its because you're missing a load of signals from the sensitivity list. X1, x2, x3, w1, w2, w3, s_x1-3, s_w1-3, en_in and s_output.

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Altera_Forum
Honored Contributor II
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Hi Tricky and Thank you very much for your help. 

 

I will try that. But, why do I need to specify in the sensitivity list internal signals too (like s_x1-3 and s_w1-3)? 

 

Please, could you tell me how do you choose which signal inside a process that need to be put in sensitivy list? 

 

My thought is that when the PS changes, the neuron_proc process is called. 

And PS changes in the first process, sync_proc.
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Altera_Forum
Honored Contributor II
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Any signal (a port is also a signal) that has an effect on any other signal inside the process must be in the sensitivity list for the simulation to match the real hardware behaviour. Synthesis ignores sensitivity lists. 

 

So anything inside an If, elseif, case statement or on the right hand side of an assignment must be in the sensitivity list., Unless it is a synchronous process, when only the clock and any asynchronous reset signals need to be in there. 

 

Processes are never "called" they execute forever, from time 0 to the end of simulation. They will be re-evaluated every time a signal in the sensitivity list changes.
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Altera_Forum
Honored Contributor II
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Instead of me doing the work for you, how about putting some signals from inside the neuron entity onto the wave form to see whats going on.

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Altera_Forum
Honored Contributor II
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Btw, I did some of the work for you - and it ran just fine for me. Are you sure the clock you show in your simulation is actually connected to the clock input? It has to be connected to pin_name8

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